AM2431BSDGHIALVR. datasheet(209/282 Pages) TI2

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6.11.5.14.1.2 OSPI0 Without Data Training

Note

Timing parameters defined in this section are only applicable when data training is not implemented

and DLL delays are configured as described in Table 6-102 and Table 6-105.

6.11.5.14.1.2.1 OSPI0 PHY SDR Timing

Table 6-102 defines DLL delays required for OSPI0 PHY SDR Mode. Table 6-103, Figure 6-81, Figure 6-82,

Table 6-104, and Figure 6-83 present timing requirements and switching characteristics for OSPI0 PHY SDR

Mode.

Table 6-102. OSPI0 DLL Delay Mapping for PHY SDR Timing Modes

MODE

DELAY VALUE

OSPI_PHY_CONFIGURATION_REG

Transmit

All modes

PHY_CONFIG_TX_DLL_DELAY_FLD

0x0

Receive

All modes

PHY_CONFIG_RX_DLL_DELAY_FLD

0x0

PHY_MASTER_CONTROL_REG

All modes

PHY_MASTER_PHASE_DETECT_SELECTOR_FLD

0x3

Table 6-103. OSPI0 Timing Requirements – PHY SDR Mode

see Figure 6-81 and Figure 6-82

NO.

MODE

MIN

MAX

UNIT

O19

tsu(D-CLK)

Setup time, OSPI0_D[7:0] valid before

active OSPI0_CLK edge

1.8V, SDR with Internal PHY Loopback

4.8

3.3V, SDR with Internal PHY Loopback

5.19

O20

th(CLK-D)

Hold time, OSPI0_D[7:0] valid after active

OSPI0_CLK edge

1.8V, SDR with Internal PHY Loopback

-0.5

3.3V, SDR with Internal PHY Loopback

-0.5

O21

tsu(D-LBCLK)

Setup time, OSPI0_D[7:0] valid before

active OSPI0_DQS edge

1.8V, SDR with External Board Loopback

0.6

3.3V, SDR with External Board Loopback

0.9

O22

th(LBCLK-D)

Hold time, OSPI0_D[7:0] valid after active

OSPI0_DQS edge

1.8V, SDR with External Board Loopback

1.7

3.3V, SDR with External Board Loopback

2.0

OSPI_CLK

OSPI_D[i:0]

OSPI_TIMING_05

O 9

O20

Figure 6-81. OSPI0 Timing Requirements – PHY SDR with Internal PHY Loopback

OSPI_DQS

OSPI_TIMING_06

O21

O 2

OSPI_D[i:0]

Figure 6-82. OSPI0 Timing Requirements – PHY SDR with External Board Loopback

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AM2434, AM2432, AM2431

SPRSP65J – APRIL 2021 – REVISED JUNE 2026

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