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AM2431BSDGHIALVR. Datasheet(PDF) 213 Page - Texas Instruments |
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AM2431BSDGHIALVR. Datasheet(HTML) 213 Page - Texas Instruments |
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213 / 282 page  6.11.5.14.2 OSPI0 Tap Mode 6.11.5.14.2.1 OSPI0 Tap SDR Timing Table 6-108, Figure 6-86, Table 6-109, and Figure 6-87 present timing requirements and switching characteristics for OSPI0 Tap SDR Mode. Table 6-108. OSPI0 Timing Requirements – Tap SDR Mode see Figure 6-86 NO. MODE MIN MAX UNIT O19 tsu(D-CLK) Setup time, OSPI0_D[7:0] valid before active OSPI0_CLK edge No Loopback (15.4 - (0.975T(1)R(2))) ns O20 th(CLK-D) Hold time, OSPI0_D[7:0] valid after active OSPI0_CLK edge No Loopback (- 4.3 + (0.975T(1)R(2))) ns (1) T = OSPI_RD_DATA_CAPTURE_REG[DELAY_FLD] (2) R = reference clock cycle time in ns OSPI_CLK OSPI_D[i:0] OSPI_TIMING_05 O 9 1 O20 Figure 6-86. OSPI0 Timing Requirements – Tap SDR, No Loopback www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 213 Product Folder Links: AM2434 AM2432 AM2431 |
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