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AM2431BSDGHIALVR. Datasheet(PDF) 239 Page - Texas Instruments

Part # AM2431BSDGHIALVR.
Description  AM243x Sitara™ Microcontrollers
PDF  282 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
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AM2431BSDGHIALVR. Datasheet(HTML) 239 Page - Texas Instruments

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6.11.6.2 JTAG
Table 6-154. JTAG Timing Conditions
PARAMETER
MIN
MAX
UNIT
INPUT CONDITIONS
SRI
Input slew rate
0.5
2.0
V/ns
OUTPUT CONDITIONS
CL
Output load capacitance
5
15
pF
PCB CONNECTIVITY REQUIREMENTS
td(Trace Delay)
Propagation delay of each trace
83.5
1000(1)
ps
td(Trace Mismatch Delay)
Propagation delay mismatch across all traces
100
ps
(1)
Maximum propagation delay associated with the JTAG signal traces has a significant impact on maximum TCK operating frequency. It
may be possible to increase the trace delay beyond this value, but the operating frequency of TCK must be reduced to account for the
additional trace delay.
Table 6-155. JTAG Timing Requirements
see Figure 6-116
NO.
MIN
MAX
UNIT
J1
tc(TCK)
Cycle time minimum, TCK
45.5(1)
ns
J2
tw(TCKH)
Pulse width minimum, TCK high
0.4P(2)
ns
J3
tw(TCKL)
Pulse width minimum, TCK low
0.4P(2)
ns
J4
tsu(TDI-TCK)
Input setup time minimum, TDI valid to TCK high
4
ns
tsu(TMS-TCK)
Input setup time minimum, TMS valid to TCK high
4
ns
J5
th(TCK-TDI)
Input hold time minimum, TDI valid from TCK high
2
ns
th(TCK-TMS)
Input hold time minimum, TMS valid from TCK high
2
ns
(1)
The maximum TCK operating frequency assumes the following timing requirements and switching characteristics for the attached
debugger. The operating frequency of TCK must be reduced to provide appropriate timing margin if the debugger exceeds any of these
assumptions.
•
Minimum TDO setup time of 2.2ns relative to the rising edge of TCK
•
TDI and TMS output delay in the range of -16.1ns to 14.1ns relative to the falling edge of TCK
(2)
P = TCK cycle time in ns
Table 6-156. JTAG Switching Characteristics
see Figure 6-116
NO.
PARAMETER
MIN
MAX
UNIT
J6
td(TCKL-TDOI)
Delay time minimum, TCK low to TDO invalid
0
ns
J7
td(TCKL-TDOV)
Delay time maximum, TCK low to TDO valid
14
ns
TDO
J2
J1
J4
TCK
J5
TDI / TMS
J3
J6
J7
J4
J5
Figure 6-116. JTAG Timing Requirements and Switching Characteristics
www.ti.com
AM2434, AM2432, AM2431
SPRSP65J – APRIL 2021 – REVISED JUNE 2026
Copyright © 2026 Texas Instruments Incorporated
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Product Folder Links: AM2434 AM2432 AM2431



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