AM2431BSDGHIALVR. datasheet(264/282 Pages) TI2

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10 Revision History

Changes from December 22, 2025 to June 3, 2026 (from Revision H (DECEMBER 2025) to

Revision I (June 2026))

Page

• Global: Added ANI package option support to the device.................................................................................1

• (Features): Added details for the new ANI package option................................................................................1

• (Device Comparison): Аdded a note clarifying that features availability may vary by package..........................7

• (Power-On Hours): Removed note referencing an application report............................................................ 104

• (Speed Grade Maximum Frequency): Added ANI package option to the table..............................................107

• (Thermal Resistance Characteristics): Added ANI package option to the table............................................. 118

• (MCU_OSC0 Switching Characteristics - Crystal Mode): Added ANI package option to the table................ 136

• (GPMC): Widened range of output load capacitance. Specified separate ranges for 133MHz Synchronous

Mode and All other modes..............................................................................................................................160

• (GPMC and NOR Flash Timing Requirements — Synchronous Mode): Simplified MODE column to include

only div_by_1_mode and not_div_by_1_mode. Changed column headers from GPMC_FCLK = 100MHz/

133MHz to 32-bit data bus (up to 100MHz)/16-bit data bus (up to 133MHz). Simplified several parameter

descriptions. Updated pin names to match Pin Attributes table. Updated the table notes. ...........................160

• (GPMC and NOR Flash Switching Characteristics – Synchronous Mode): Removed the MODE column.

Combined the GPMC_FCLK=100MHz and GPMC_FCLK=133MHz columns. Reduced F2 and F3 clk-csn

maximum output delays. Changed the timing variable in parameters F3 and F11 to "D". Removed 2 of the F7

rows. Removed the "J" timing variable from the F15 and F17 parameters. Added byte enables for 32-bit data

bus to F6, F7, F17, F19. Simplified several parameter descriptions. Updated pin names to match Pin

Attributes table. Updated the table notes....................................................................................................... 160

• (GPMC and NOR Flash Timing Requirements – Asynchronous Mode): Removed the MODE column and the

table note that described register configuration for div_by_1_mode. Added the correct table note for

parameter FA21 .............................................................................................................................................169

• (GPMC and NOR Flash Switching Characteristics – Asynchronous Mode): Removed the MODE column and

redundant rows. Also removed the table note that described register configuration for div_by_1_mode. Moved

links to table notes directly next to each letter. ..............................................................................................169

• (GPMC and NAND Flash Timing Requirements – Asynchronous Mode): Removed the MODE column and the

table note that described register configuration for div_by_1_mode.............................................................. 176

• (GPMC and NAND Flash Switching Characteristics – Asynchronous Mode): Removed the MODE column and

the table note that described register configuration for div_by_1_mode. Added table notes and associated

reference links for timing variables A, B, C, D, E, F, G, H, I, K, L, and M.......................................................176

• (MCSPI Switching Characteristics – Peripheral Mode): Updated values for parameters SS6 and SS7........ 187

• (Device Naming Convention): Updated Package Designator row (added ANI package option).................... 261

AM2434, AM2432, AM2431

SPRSP65J – APRIL 2021 – REVISED JUNE 2026

www.ti.com

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AM2431BSDGHIALVR. Datasheet(PDF) 264 Page - Texas Instruments

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