AM2431BSDGHIALVR. datasheet(125/282 Pages) TI2

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6.11.2.2.2 Power-Down Sequencing

Table 6-6 and Figure 6-6 describe the device power-down sequencing.

Note

All power rails must be turned off and decay below 300mV before initiating a new power-up sequence

anytime a power rail drops below the minimum value defined in Recommended Operating Conditions.

Table 6-6. Power-Down Sequencing – Supply / Signal Assignments

See: Figure 6-6

WAVEFORM

SUPPLY / SIGNAL NAME

VSYS, VMON_VSYS

VDDSHV_MCU(1), VDDSHV0(1), VDDSHV1(1), VDDSHV2(1), VDDSHV3(1), VDDSHV4(1),VDDA_3P3_USB0,

VMON_3P3_SOC, VMON_3P3_MCU

VDDSHV_MCU(2), VDDSHV0(2), VDDSHV1(2), VDDSHV2(2), VDDSHV3(2), VDDSHV4(2), VDDA_MCU,

VDDS_OSC, VDDA_ADC0, VDDA_PLL0, VDDA_PLL1, VDDA_PLL2, VDDA_1P8_SERDES0, VDDA_1P8_USB0,

VMON_1P8_SOC, VMON_1P8_MCU, VDDA_TEMP0, VDDA_TEMP1, VDDS_MMC0

VDDA_3P3_SDIO(3) (4), VDDSHV5(3)

VDDS_DDR(5), VDDS_DDR_C(5)

VDD_CORE(6), VDDA_0P85_USB0(6), VDDA_0P85_SERDES0(6), VDDA_0P85_SERDES0_C(6), VDD_MMC0(6),

VDDA_DLL_MMC0(6), VDDR_CORE(6)

VPP

MCU_PORz

MCU_OSC0_XI, MCU_OSC0_XO

(1)

VDDSHV_MCU and VDDSHVx [x=0-4] when operating at 3.3V.

(2)

VDDSHV_MCU and VDDSHVx [x=0-4] when operating at 1.8V.

(3)

VDDA_3P3_SDIO was designed to support power-up or power-down without any dependency on other power rails. VDDSHV5 is a

dual voltage IO supply that was designed to support power-up, power-down, or dynamic voltage change without any dependency on

other power rails. This capability is required to support UHS-I SD Cards.

(4)

VDDA_3P3_SDIO is the 3.3V power rail for the internal SDIO_LDO. This power rail must be sourced from the same 3.3V power supply

that provides power to a UHS-I SD Card connected to MMC1, which allows the MMC1 IOs and the SD Card IOs to power-up and

power-down at the same time when the SD Card power supply is powered off to reset the SD Card. For this use case the SDIO_LDO

output (CAP_VDDSHV_MMC1) is used to power the VDDSHV5 IO power rail, which will ramp-up and ramp-down along with the

VDDA_3P3_SDIO power rail.

(5)

VDDS_DDR and VDDS_DDR_C are expected to be powered by the same source such that they ramp together.

(6)

VDD_CORE, VDDA_0P85_USB0, VDDA_0P85_SERDES0, VDDA_0P85_SERDES0_C, VDD_MMC0, VDDA_DLL_MMC0, and

VDDR_CORE are expected to be powered by the same 0.85V source such that they ramp together.

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AM2434, AM2432, AM2431

SPRSP65J – APRIL 2021 – REVISED JUNE 2026

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