RZSLASHG2H datasheet(3/169 Pages) RENESAS

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RZ/G Series, 2nd Generation Datasheet

Section 1 Overview

R01DS0483EJ0101 Rev.1.01

Page 3 of 169

Jun 30, 2025

1.1.2

CPU Core Peripherals

Item

Description

Clock Pulse Generator (CPG)

(For All Products)

• Generates the clocks from external clock (EXTAL).

RZ/G2H RZ/G2M V1.3 RZ/G2M V3.0 RZ/G2N

— Maximum Cortex-A57 clock: 1.5 GHz

RZ/G2H RZ/G2M V1.3 RZ/G2M V3.0 RZ/G2E

⎯ Maximum Cortex-A53 clock: 1.2 GHz

RZ/G2H RZ/G2M V1.3 RZ/G2M V3.0 RZ/G2N RZ/G2E

⎯ Maximum 3DGE clock: 600 MHz

RZ/G2H RZ/G2M V1.3 RZ/G2M V3.0 RZ/G2N

⎯ Maximum AXI-bus clock: 400 MHz

⎯ Maximum SDRAM bus clock: 1600 MHz (LPDDR4-3200)

⎯ Maximum media clock: 400 MHz

RZ/G2E

⎯ Maximum AXI-bus clock: 266 MHz

⎯ Maximum SDRAM bus clock: 928 MHz (DDR3L-1856)

⎯ Maximum media clock: 266 MHz

RZ/G2H RZ/G2M V1.3 RZ/G2M V3.0 RZ/G2N RZ/G2E

• System-CPU shut down mode control supported

• Module-standby mode supported

• Includes module reset registers to control reset operation of individual on-chip

peripheral modules

System Controller (SYSC)

(For All Products)

• Shuts down and restores power to target modules

Target modules:

RZ/G2H

— Cortex-A57 (with independent shutting down of CPUs 0, 1, 2, 3, and SCU+L2

cache) *

RZ/G2M V1.3 RZ/G2M V3.0 RZ/G2N

— Cortex-A57 (with independent shutting down of CPUs 0, 1 and SCU+L2 cache) *

RZ/G2H RZ/G2M V1.3 RZ/G2M V3.0

— Cortex-A53 (with independent shutting down of CPUs 0, 1, 2, 3, and SCU+L2

cache) *

— 3DGE

— VCP

RZ/G2E

— Cortex-A53 (with independent shutting down of CPUs 0, 1 and SCU+L2 cache) *

*: SCU and L2 cache are treated as one power-domain. When CPU is working,

SCU+L2 cache cannot be powered off.

• Low leakage standby mode supported

RESET

(For All Products)

• Includes one reset-signal external output port for external modules

• Includes Boot Address Register, etc.

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