RZSLASHG2H datasheet(5/169 Pages) RENESAS

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RZ/G Series, 2nd Generation Datasheet

Section 1 Overview

R01DS0483EJ0101 Rev.1.01

Page 5 of 169

Jun 30, 2025

1.1.3

External Bus Module

Item

Description

External Bus

Controller for EX-

Bus (LBSC)

(For All Products)

• EX-BUS interface: max. 16-bit bus

RZ/G2H RZ/G2M V1.3 RZ/G2M V3.0 RZ/G2N

• Frequency: 66 MHz or 44.4 MHz

RZ/G2E

• Frequency: 66 MHz

RZ/G2H RZ/G2M V1.3 RZ/G2M V3.0 RZ/G2N RZ/G2E

• External area divided into several areas and managed

— Allocation to space of area 0, area 1

— Area 0 supports 1-MByte memory space (startup mode).

— I/F settings, bus width settings, and wait state insertion are possible for each area.

• SRAM interface

— Wait states can be inserted through register settings.

Period of waiting is set in cycle unit, and the maximum value is 15.

— EX_WAIT pin can be used for wait state insertion.

— Connectable bus widths: 16 bits or 8 bits

• Supports external buffer enable/direction control

• Supports Burst ROM interface

• Supports Byte-control SRAM interface

External Flash

Controller

(For All Products)

• Supports RPC-IF (Reduced Pin Count interface) flash memory or QSPI flash memory

RZ/G2H RZ/G2M V1.3 RZ/G2M V3.0 RZ/G2N

Max. Frequency 160 MHz (320MB/s) for RPC-IF, 80 MHz (80MB/s)* for QSPI (QSPI0)

RZ/G2E

Max. Frequency 150 MHz (300MB/s) for RPC-IF, 80 MHz (80MB/s) for QSPI (QSPI0)

RZ/G2H RZ/G2M V1.3 RZ/G2M V3.0 RZ/G2N RZ/G2E

Dual QSPI operation for two 4-bit serial flash memories is also available; 80 MHz (160MB/s)*

for Dual QSPI (QSPI0+QSPI1).

Note. *: For RZ/G2M V1.3, 40MB/s for QSPI, 80MB/s for dual QSPI.

The RZ/G2M V1.3 does not support QSPI-DDR operation.

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