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RZ/G2H Datasheet(PDF) 78 Page - Renesas Technology Corp |
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RZ/G2H Datasheet(HTML) 78 Page - Renesas Technology Corp |
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78 / 169 page ![]() RZ/G Series, 2nd Generation Datasheet Section 3. Electrical Characteristics R01DS0483EJ0101 Rev.1.01 Page 78 of 169 Jun 30, 2025 3.6 EXTAL Clock Input/output Timing 3.6.1 EXTAL Clock Input Timing Table 3.6.1 EXTAL Clock Input Timing Conditions: VDDQ18 = 1.8 V ± 0.1 V, GND = VSS = 0 V, Tc = -40 to +115 °C[RZ/G2H, RZ/G2M V1.3], Ta = -40 to +85 °C[RZ/G2M V3.0, RZ/G2N], Tj = -40 to +115 °C[RZ/G2M V3.0, RZ/G2N] Item Symbol Min. Typ. Max. Unit Figures EXTAL clock input frequency MD[14:13] = LL fEX 14.40 16.66 16.70 MHz — MD[14:13] = LH 17.30 20.00 20.04 MHz MD[14:13] = HL 21.62 25.00 25.06 MHz MD[14:13] = HH 28.80 33.33 33.40 MHz EXTAL clock input cycle time MD[14:13] = LL tEXcyc 59.88 60.02 69.44 ns Figure 3.6.1 MD[14:13] = LH 49.90 50.00 57.80 ns MD[14:13] = HL 36.90 40.00 46.25 ns MD[14:13] = HH 29.94 30.00 34.72 ns EXTAL clock input duty cycle time tEXduty 0.4 0.5 0.6 tEXcyc EXTAL clock input low-level pulse width tEXL 5 — — ns EXTAL clock input high-level pulse width tEXH 5 — — ns EXTAL clock input rise time tEXr — — 4 ns EXTAL clock input fall time tEXf — — 4 ns Note: Set the MD9 pin to L (low) during power-on reset when using the EXTAL pin as external clock input and the XTAL pin must be open. Not to exceed the specification of LPDDR4 operating frequency, input the lower frequency of EXATL or lower the multiplication rate of PLL. Figure 3.6.1 EXTAL Clock Input Timing EXTAL (input) 1/2VDDQ18 VIH VIH VIH VIL VIL 1/2VDDQ18 tEXcyc tEXduty tEXduty tEXH tEXL tEXf tEXr RZ/G2H RZ/G2M V1.3 RZ/G2N RZ/G2E RZ/G2M V3.0 |
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