RZSLASHG2H datasheet(7/169 Pages) RENESAS

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RZ/G Series, 2nd Generation Datasheet

Section 1 Overview

R01DS0483EJ0101 Rev.1.01

Page 7 of 169

Jun 30, 2025

1.1.4

Internal Bus Module

Item

Description

AXI-bus

(For All Products)

• On-chip main bus

— Bus protocol: AXI3 with QoS control

RZ/G2H RZ/G2M V1.3 RZ/G2M V3.0 RZ/G2N

— Frequency: 400 MHz

— Bus width: 512 bits/256 bits/128 bits

RZ/G2E

— Frequency: 266 MHz

— Bus width: 256 bits/128 bits/64 bits

• On-chip CPU bus

RZ/G2H RZ/G2M V1.3 RZ/G2M V3.0

— CoreLink™ CCI-Kipling Cache Coherent Interconnect

— Bus protocol: AMBA®4 ACE™ and ACE-Lite™

— Frequency: 800 MHz

— Bus width: 128 bits

RZ/G2N

— Bus protocol: AXI3

— Frequency: 800 MHz

— Bus width: 128 bits

RZ/G2E

— Bus protocol: AXI3

— Frequency: 533 MHz

— Bus width: 128 bits

Direct Memory Access

Controller for System

(SYS-DMAC)

(For All Products)

• 16 channels for PeriW domain (SYDM0)

• 32 channels for PeriE domain (SYDM1, 2)

• Address space: 4 GBytes on architecture

• Data transfer length: Byte, word (2 Bytes), longword (4 Bytes), 8 Bytes, 16 Bytes, 32 Bytes

and 64 Bytes

• Maximum number of transfer times: 16,777,215 times

• Transfer request:

Selectable from on-chip peripheral module request and auto request

• Bus mode:

Selectable from normal mode and slow mode

• Priority: Selectable from fixed channel priority mode and round-robin mode

• Interrupt request: Supports interrupt request to CPU at the end of data transfer

• Repeat function: Automatically resets the transfer source, destination, and count at the

end of DMA transfer (by descriptor function)

• Descriptor function (each channel) supported

• MMU (each channel) supported

• Channel bandwidth arbiter (each channel)

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