8SLVP1212 datasheet(13/24 Pages) RENESAS

13 / 24 page

R31DS0036EU0300 MAY 20, 2021

8SLVP1212 Datasheet

3.3V LVPECL Clock Input Interface

The PCLK /nPCLK accepts LVPECL, LVDS, CML and other

differential signals. Both differential outputs must meet the VPP and

VCMR input requirements. Figures 2A to 2E show interface examples

for the PCLK/ nPCLK input driven by the most common driver types.

The input interfaces suggested here are examples only. If the driver

is from another vendor, use their termination recommendation.

Please consult with the vendor of the driver component to confirm the

driver termination requirements.

Figure 2A. PCLK/nPCLK Input Driven by a CML Driver

Figure 2C. PCLK/nPCLK Input Driven by a

3.3V LVPECL Driver

Figure 2E. PCLK/nPCLK Input Driven by a

3.3V LVDS Driver

Figure 2B. PCLK/nPCLK Input Driven by a

Built-In Pullup CML Driver

Figure 2D. PCLK/nPCLK Input Driven by a

3.3V LVPECL Driver with AC Couple

PCLK

nPCLK

LVPECL

Input

CML

3.3V

125

3.3V

Zo = 50

PCLK

nPCLK

3.3V

LVPECL

Input

3.3V

100

LVDS

PCLK

nPCLK

3.3V

LVPECL

Input

Zo = 50

PCLK

nPCLK

3.3V

LVPECL

Input

3.3V

Zo = 50

100

CML Built-In Pullup

8SLVP1212 Datasheet(PDF) 13 Page - Renesas Technology Corp

8SLVP1212 Datasheet(HTML) 13 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datasheet Download

Link URL