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EM78P342NP Datasheet(PDF) 29 Page - ELAN Microelectronics Corp |
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EM78P342NP Datasheet(HTML) 29 Page - ELAN Microelectronics Corp |
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29 / 102 page ![]() EM78P341N/342N/343N 8-Bit Microprocessor with OTP ROM Product Specification (V1.0) 12.01.2006 • 23 (This specification is subject to change without further notice) Bit 4 (/OD64): Control bit used to enable the open-drain of the P64 pin (Not applicable to EM78P341N) Bit 3 (/OD63): Control bit used to enable the open-drain of the P63 pin (Not applicable to EM78P341N) Bit 2 (/OD62): Control bit used to enable the open-drain of the P62 pin (Not applicable to EM78P341N) Bit 1 (/OD61): Control bit used to enable the open-drain of the P61 pin Bit 0 (/OD60): Control bit used to enable the open-drain of the P60 pin 6.2.9 IOCD0 (Pull-high Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 /PH57 /PH56 /PH55 /PH54 /PH53 /PH52 /PH51 /PH50 NOTE The IOCD0 register is both readable and writable. Bit 7 (/PH57): Control bit is used to enable the pull-high of the P57 pin (applicable to EM78P343N only). 0 = Enable internal pull-high 1 = Disable internal pull-high Bit 6 (/PH56): Control bit used to enable the pull-high function of the P56 pin (applicable to EM78P343N only). Bit 5 (/PH55): Control bit used to enable the pull-high function of the P55 pin. Bit 4 (/PH54): Control bit used to enable the pull-high function of the P54 pin. Bit 3 (/PH53): Control bit used to enable the pull-high function of the P53 pin. Bit 2 (/PH52): Control bit used to enable the pull-high function of the P52 pin. Bit 1 (/PH51): Control bit used to enable the pull-high function of the P51 pin. Bit 0 (/PH50): Control bit used to enable the pull-high function of the P50 pin. 6.2.10 IOCE0 (WDT Control & Interrupt Mask Registers 2) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WDTE EIS ADIE CMPIE PSWE PSW2 PSW1 PSW0 Bit 7 (WDTE): Control bit used to enable Watchdog Timer 0 = Disable WDT 1 = Enable WDT WDTE is both readable and writable. |
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