ADMV4530 datasheet(8/64 Pages) AD

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Data Sheet

ADMV4530

ABSOLUTE MAXIMUM RATINGS

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Rev. C | 8 of 64

Figure 2. Circuit Level Description of Power Map (Left) and Uniform Power

Dissipation Methods (Right)

Table 5. Thermal Rise from Case to Junction

Operational Mode

ΔTJC

Unit

IF and I/Q mode

°C

The thermal resistance of the ADMV4530 assuming the JE-

DEC standard of uniform power dissipation based on a JEDEC

(JESD51-2) board is shown in Table 6. Thermal resistance based

on a uniform power dissipation is useful to compare the perform-

ance of the ADMV4530 to other similar ICs.

Table 6. Thermal Resistance

Package Type

θJC_BOT1

θJC_TOP1

ΨJT

ΨJB

θJA

Unit

CC-40-8

3.9

11.7

3.0

8.5

28.2

°C/W

1 See JEDEC Standard JESD51-2 for additional information on optimizing the

thermal impedance.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Charged devi-

ces and circuit boards can discharge without detection. Although

this product features patented or proprietary protection circuitry,

damage may occur on devices subjected to high energy ESD.

Therefore, proper ESD precautions should be taken to avoid

performance degradation or loss of functionality.

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