ADSP-CM403CSWZ-CF datasheet(55/124 Pages) AD

55 / 124 page

Rev. A

Page 55 of 124

November 2015

ADSP-CM402F/CM403F/CM407F/CM408F/CM409F

PA_15

I/O

pu or

none

VDD_EXT

Desc: PA Position 15 | PWM1 Channel B Low Side | TM0 Timer

3 | SMC0 Data 7

Notes: By default, the internal termination pull-up is active.

The state of pull-ups can be configured by configuring the

PORT_INEN and PADS_PCFG0 registers.

PB_00

I/O

pu or

none

VDD_EXT

Desc: PB Position 0 | PWM0 Channel D High Side | Embedded

Trace Module Clock | SPORT0 Channel A Clock | SMC0 Data 8

| CNT0 Count Zero Marker

Notes: By default, the internal termination pull-up is active.

The state of pull-ups can be configured by configuring the

PORT_INEN and PADS_PCFG0 registers.

PB_01

I/O

pu or

none

VDD_EXT

Desc: PB Position 1 | PWM0 Channel D Low Side | Embedded

Trace Module Data 0 | SPORT0 Channel A Frame Sync | SMC0

Data 9 | CNT0 Count Up and Direction

Notes: By default, the internal termination pull-up is active.

The state of pull-ups can be configured by configuring the

PORT_INEN and PADS_PCFG0 registers.

PB_02

I/O

pu or

none

VDD_EXT

Desc: PB Position 2 | PWM1 Channel D High Side | Embedded

Trace Module Data 1 | SPORT0 Channel A Data 0 | SMC0 Data

10 | CNT0 Count Down and Gate

Notes: By default, the internal termination pull-up is active.

The state of pull-ups can be configured by configuring the

PORT_INEN and PADS_PCFG0 registers.

PB_03

I/O

pu or

none

VDD_EXT

Desc: PB Position 3 | PWM1 Channel D Low Side | Embedded

Trace Module Data 2 | SPORT0 Channel A Data 1 | SMC0 Data

11 | CNT1 Count Zero Marker

Notes: By default, the internal termination pull-up is active.

The state of pull-ups can be configured by configuring the

PORT_INEN and PADS_PCFG0 registers.

PB_04

I/O

pu or

none

VDD_EXT

Desc: PB Position 4 | PWM2 Sync | UART0 Request to Send |

SPORT0 Channel A Transmit Data Valid | SMC0 Data 12 | CNT1

Count Up and Direction

Notes: By default, the internal termination pull-up is active.

The state of pull-ups can be configured by configuring the

PORT_INEN and PADS_PCFG0 registers.

PB_05

I/O

pu or

none

VDD_EXT

Desc: PB Position 5 | PWM2 Trip Input 0 | UART0 Clear to Send

| TM0 Timer 7 | SMC0 Data 13 | CNT1 Count Down and Gate

Notes: By default, the internal termination pull-up is active.

The state of pull-ups can be configured by configuring the

PORT_INEN and PADS_PCFG0 registers.

PB_06

I/O

pu or

none

VDD_EXT

Desc: PB Position 6 | PWM2 Channel A High Side | TM0

Common Clock | SPI1 Slave Select Output 2 | SMC0 Data 14

Notes: By default, the internal termination pull-up is active.

The state of pull-ups can be configured by configuring the

PORT_INEN and PADS_PCFG0 registers.

PB_07

I/O

pu or

none

VDD_EXT

Desc: PB Position 7 | PWM2 Channel A Low Side | TM0 Timer 0

| SPI1 Slave Select Output 3 | SMC0 Data 15 | Capture Timer0

Input 0

Notes: By default, the internal termination pull-up is active.

The state of pull-ups can be configured by configuring the

PORT_INEN and PADS_PCFG0 registers.

Table 25. ADSP-CM40xF Designer Quick Reference (Continued)

Signal Name

Type

Driver

Type

Int

Term

Reset

Term

Reset

Drive

Power

Domain

Description

and Notes

ADSP-CM403CSWZ-CF Datasheet(PDF) 55 Page - Analog Devices

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