ADSP-CM403CSWZ-CF datasheet(16/124 Pages) AD

16 / 124 page

Rev. A

Page 16 of 124

November 2015

ADSP-CM402F/CM403F/CM407F/CM408F/CM409F

Full-On Operating Mode—Maximum Performance

In the full-on mode, the PLL is enabled and is not bypassed,

providing capability for maximum operational frequency. This

is the execution state in which maximum performance can be

achieved. The processor core and all enabled peripherals run at

full speed.

For more information about PLL controls, see the “Dynamic

Power Management” chapter in the ADSP-CM40x Mixed-Signal

Control Processor with ARM Cortex-M4 Hardware Reference.

Deep Sleep Operating Mode—Maximum Dynamic Power

Savings

The deep sleep mode maximizes dynamic power savings by dis-

abling the clocks to the processor core and to all synchronous

peripherals. Asynchronous peripherals may still be running but

cannot access internal resources or external memory.

Voltage Regulation for VDD_INT

The internal voltage VDD_INT to the ADSP-CM40xF proces-

sors can be generated either by using an on-chip voltage

regulator or by an external voltage regulator.

The VDD_INT of 1.2 V can be generated using the external I/O

supply VDD_VREG of 3.3 V, which is then used to generate

VDD_INT of 1.2 V. Figure 9 shows the external components

required to complete the power management system for proper

operation. For more details regarding component selection,

refer to (EE-361) ADSP-CM40x Power Supply Transistor Selec-

tion Guidelines (www.analog.com/ee-361).

The internal voltage regulator can be bypassed and VDD_INT

can be supplied using an external regulator. When an external

regulator is used, VDD_VREG and VREG_BASE must be tied

to ground for zero current consumption.

Reset Control Unit (RCU)

Reset is the initial state of the whole processor or of the core and

is the result of a hardware or software triggered event. In this

state, all control registers are set to their default values and func-

tional units are idle. Exiting a core only reset starts with the core

being ready to boot.

The reset control unit (RCU) controls how all the functional

units enter and exit reset. Differences in functional require-

ments and clocking constraints define how reset signals are

generated. Programs must guarantee that none of the reset

functions puts the system into an undefined state or causes

resources to stall.

From a system perspective reset is defined by both the reset tar-

get and the reset source as described below.

Target defined:

• Hardware Reset—All functional units are set to their

default states without exception. History is lost.

• System Reset—All functional units except the RCU are set

to their default states.

Source defined:

• Hardware Reset—The SYS_HWRST input signal is

asserted active (pulled down).

• System Reset—May be triggered by software (writing to the

RCU_CTL register) or by another functional unit such as

the dynamic power management (DPM) unit or any of the

system event controller (SEC), trigger routing unit (TRU),

or emulator inputs.

• Trigger request (peripheral).

SYSTEM DEBUG UNIT (SDU)

The processor includes various features that allow for easy sys-

tem debug. These are described in the following sections.

JTAG Debug and Serial Wire Debug Port (SWJ-DP)

SWJ-DP is a combined JTAG-DP and SW-DP that enables

either a serial wire debug (SWD) or JTAG probe to be con-

nected to a target. SWD signals share the same pins as JTAG.

There is an auto detect mechanism that switches between

JTAG-DP and SW-DP depending on which special data

sequence is used the emulator pod transmits to the JTAG

pins.The SWJ-DP behaves as a JTAG target if normal JTAG

sequences are sent to it and as a single wire target if the SW_DP

sequence is transmitted.

Embedded Trace Macrocell (ETM) and Instrumentation

Trace Macrocell (ITM)

The ADSP-CM40xF processors support both embedded trace

macrocell (ETM) and instrumentation trace macrocell (ITM).

These both offer an optional debug component that enables log-

ging of real-time instruction and data flow within the CPU core.

This data is stored and read through special debugger pods that

have the trace feature capability. The ITM is a single-data pin

feature and the ETM is a 4-data pin feature.

System Watchpoint Unit (SWU)

The system watchpoint unit (SWU) is a single module which

connects to a single system bus and provides for transaction

monitoring. One SWU is attached to the bus going to each

system slave. The SWU provides ports for all system bus address

channel signals. Each SWU contains four match groups of

Figure 9. Internal Voltage Regulator Circuit

DD_VREG

STD2805T4

REG_BASE

DD_INT

3.3V

10 - 220μF

0.1μF

DD_VREG

STD2805T4

REG_BASE

DD_INT

3.3V

10 - 220μF

0.1μF

DD_VREG

STD2805T4

REG_BASE

DD_INT

3.3V

10 - 220μF

0.1μF

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