| Electronic Components Datasheet Search |
|
ADSP-CM403CSWZ-CF Datasheet(PDF) 89 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
ADSP-CM403CSWZ-CF Datasheet(HTML) 89 Page - Analog Devices |
|
89 / 124 page ![]() Rev. A | Page 89 of 124 | November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Serial Peripheral Interface (SPI) Port—Master Timing Table 47 and Figure 35 describe serial peripheral interface (SPI) port master operations.When internally generated, the programmed SPI clock (fSPICLKPROG) frequency in MHz is set by the following equation where BAUD is a field in the SPI_CLK register that can be set from 0 to 65,535: Note that: • In dual mode data transmit, the SPI_MISO signal is also an output. • In quad mode data transmit, the SPI_MISO, SPI_D2, and SPI_D3 signals are also outputs. • In dual mode data receive, the SPI_MOSI signal is also an input. • In quad mode data receive, the SPI_MOSI, SPI_D2, and SPI_D3 signals are also inputs. Table 47. Serial Peripheral Interface (SPI) Port—Master Timing Parameter Min Max Unit Timing Requirements tSSPIDM Data Input Valid to SPI_CLK Edge (Data Input Setup) 3.2 ns tHSPIDM SPI_CLK Sampling Edge to Data Input Invalid 1.3 ns Switching Characteristics tSDSCIM SPI_SEL low to First SPI_CLK Edge for CPHA = 1 1 1 Whichever is greater. [tSCLK – 2] or [18] ns SPI_SEL low to First SPI_CLK Edge for CPHA = 0 1 [1.5 × tSCLK – 2] or [13] ns tSPICHM SPI_CLK High Period 2 2 See Table 27 Clock Related Operating Conditions for details on the minimum period that may be programmed for tSPICLKPROG. 0.5 × tSPICLKPROG – 1 ns tSPICLM SPI_CLK Low Period 2 0.5 × tSPICLKPROG – 1 ns tSPICLK SPI_CLK Period2 tSPICLKPROG – 1 ns tHDSM Last SPI_CLK Edge to SPI_SEL High for CPHA = 1 1 [1.5 × tSCLK –2] or [13] ns Last SPI_CLK Edge to SPI_SEL High for CPHA = 0 1 [tSCLK –2] or [18] ns tSPITDM Sequential Transfer Delay 1, 3 3 Applies to sequential mode with STOP ≥ 1. [tSCLK – 1] or [19] ns tDDSPIDM SPI_CLK Edge to Data Out Valid (Data Out Delay) 2.6 ns tHDSPIDM SPI_CLK Edge to Data Out Invalid (Data Out Hold) –1.5 ns fSPICLKPROG fSCLK BAUD 1 + ------------------------------- = tSPICLKPROG 1 fSPICLKPROG --------------------------------- = |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |