ADSP-CM403CSWZ-CF datasheet(12/124 Pages) AD

12 / 124 page

Rev. A

Page 12 of 124

November 2015

ADSP-CM402F/CM403F/CM407F/CM408F/CM409F

The timer unit can be used in conjunction with the UARTs and

the CAN controller to measure the width of the pulses in the

data stream to provide a software auto-baud detect function for

the respective serial channels.

The timer can generate interrupts to the processor core, provid-

ing periodic events for synchronization to either the system

clock or to external signals. Timer events can also trigger other

peripherals via the TRU (for instance, to signal a fault).

Watchdog Timer (WDT)

The core includes a 32-bit timer, which may be used to imple-

ment a software watchdog function. A software watchdog can

improve system availability by forcing the processor to a known

state, via generation of a general-purpose interrupt, if the timer

expires before being reset by software. The programmer initial-

izes the count value of the timer, enables the appropriate

interrupt, then enables the timer. Thereafter, the software must

reload the counter before it counts to zero from the pro-

grammed value. This protects the system from remaining in an

unknown state where software, which would normally reset the

timer, has stopped running due to an external noise condition

or software error. Optionally, the fault management unit (FMU)

can directly initiate the processor reset upon the watchdog

expiry event.

Capture Timer (CPTMR)

The processor includes three instants of capture timers

(CPTMR) to capture total on time. Each capture timer captures

total on time of the input signal between two leading edges of

the input trigger signal. Capture timer inputs to all the timers

come from external pins and the input trigger signal comes

from trigger routing unit (TRU).

The core of the timer is a 32-bit counter which is reset at leading

edge of the trigger and counts when the input signal level is

active. The total on time of the input signal is captured from the

counter at the leading edge of the trigger pulse. Capture timer

can generate data interrupts to the processor core at leading

edges of trigger pulses and status interrupts to indicate counter

overflow condition.

3-Phase Pulse Width Modulator Unit (PWM)

The pulse width modulator (PWM) unit provides duty cycle

and phase control capabilities to a resolution of one system

clock cycle (SCLK). The heightened precision PWM (HPPWM)

module provides increased performance to the PWM unit by

increasing its resolution by several bits, resulting in enhanced

precision levels. Additional features include:

• 16-bit center-based PWM generation unit

•Programmable PWM pulse width

• Single/double update modes

• Programmable dead time and switching frequency

• Twos-complement implementation which permits smooth

transition to full on and full off states

• Dedicated asynchronous PWM trip signal

The eight PWM output signals (per PWM unit) consist of four

high-side drive signals and four low-side drive signals. The

polarity of a generated PWM signal can be set with software, so

that either active high or active low PWM patterns can be

produced.

Each PWM block integrates a flexible and programmable

3-phase PWM waveform generator that can be programmed to

generate the required switching patterns to drive a 3-phase

voltage source inverter for ac induction motor (ACIM) or per-

manent magnet synchronous motor (PMSM) control. In

addition, the PWM block contains special functions that con-

siderably simplify the generation of the required PWM

switching patterns for control of the electronically commutated

motor (ECM) or permanent magnet synchronous motor

(PMSM) control. Software can enable a special mode for

switched reluctance motors (SRM).

Each PWM unit features a dedicated asynchronous trip pin

which (when brought low) instantaneously places all PWM out-

puts in the off state.

Serial Ports (SPORTs)

The synchronous serial ports provide an inexpensive interface

to a wide variety of digital and mixed-signal peripheral devices

such as Analog Devices, Inc., audio codecs, ADCs, and DACs.

The serial ports are made up of two data lines per direction, a

clock, and frame sync. The data lines can be programmed to

either transmit or receive and each data line has a dedicated

DMA channel.

Serial port data can be automatically transferred to and from

on-chip memory/external memory via dedicated DMA chan-

nels.For full-duplex operation, two half SPORTs can work in

conjunction with clock and frame sync signals shared internally

through the SPMUX block. In some operation modes, SPORT

supports gated clock.

Serial ports operate in six modes:

• Standard DSP serial mode

•Multichannel (TDM) mode

•I2S mode

•Packed I2S mode

• Left-justified mode

•Right-justified mode

General-Purpose Counters

The 32-bit counter can operate in general-purpose up/down

count modes and can sense 2-bit quadrature or binary codes as

typically emitted by industrial drives or manual thumbwheels.

Count direction is either controlled by a level-sensitive input

pin or by two edge detectors.

A third counter input can provide flexible zero marker support

and can alternatively be used to input the push-button signal of

thumb wheels. All three pins have a programmable debouncing

circuit.

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