ADSP-CM403CSWZ-CF datasheet(80/124 Pages) AD

80 / 124 page

Rev. A

Page 80 of 124

November 2015

ADSP-CM402F/CM403F/CM407F/CM408F/CM409F

Asynchronous Page Mode Read

Table 38 and Figure 28 show asynchronous memory page mode read timing, related to the static memory controller (SMC).

Table 38. Asynchronous Page Mode Read

Parameter

Min

Max

Unit

Switching Characteristics

tAV

SMC0_Ax (Address) Valid for First Address Min Width1

1 PREST, RST, PREAT and RAT values set using the SMC_BxETIM.PREST bits, SMC_BxTIM.RST bits, SMC_BxETIM.PREAT bits, and the SMC_BxTIM.RAT bits.

(PREST + RST + PREAT + RAT) × tSCLK – 2

tAV1

SMC0_Ax (Address) Valid for Subsequent SMC0_Ax

(Address) Min Width

PGWS × tSCLK – 2

tWADV

SMC0_AOE Active Low Width2

2 RST value set using the SMC_BxTIM.RST bits.

RST × tSCLK – 3

tHARE

Output3 Hold After SMC0_ARE High4

3 Output signals are SMC0_Ax, SMC0_AMSx.

4 RHT value set using the SMC_BxTIM.RHT bits.

RHT × tSCLK – 2

tWARE

5 SMC_BxCTL.ARDYEN bit = 0.

SMC0_ARE Active Low Width6

6 RAT value set using the SMC_BxTIM.RAT bits.

RAT × tSCLK – 2

Figure 28. Asynchronous Page Mode Read

SMC0_AMSx

(NOR_CE)

SMC0_ARE

(NOR_OE)

SMC0_AOE

(NOR_ADV)

SMC0_Dx

(DATA)

tWADV

tWARE

tHARE

A0 + 1

A0 + 2

A0 + 3

tAV

tAV1

READ

LATCHED

DATA

READ

LATCHED

DATA

READ

LATCHED

DATA

READ

LATCHED

DATA

SMC0_Ax

(ADDRESS)

ADSP-CM403CSWZ-CF Datasheet(PDF) 80 Page - Analog Devices

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