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ST52T301 Datasheet(PDF) 19 Page - STMicroelectronics |
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ST52T301 Datasheet(HTML) 19 Page - STMicroelectronics |
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19 / 100 page ![]() 2.5 ARITHMETIC LOGIC UNIT The 8-bit Arithmetic Logic Unit (ALU) allows to per fo rm ar it hme tic calcu la tions and logic instructions which can be divided into 4 groups: Load, Arithmetic, Jump and Program Control instructions (refer to the ST52x301 Assembler Set for further details ). Load Instructions Menmonic Instruction Bytes Cycles Z S LDCF LDCF conf, const 2 6 - - LDRC LDRC reg, const 2 6 - - LDRI LDRI reg, inp 2 6 - - LDPR LDPR per, reg 1 6 - - LDRR LDRR regi, regj 2 6 - - Arithmetic Instructions Mnemonic Instruction Bytes Cycles Z S ADD ADD regi, regj 2 7 I I AND AND regi, regj 2 7 I - SUB SUB regi, regj 2 7 I I SUBO SUBO regi, regj 2 7 I I Jump Instructions Mnemonic Instruction Bytes Cycles Z S JP JP addr 2 6 - - JPNS JPNS addr 2 6 - - JPNZ JPNZ addr 2 6 - - JPS JPS addr 2 6 - - JPZ JPZ addr 2 6 - - SCI Instructions Mnemonic Instruction Bytes Cycles Z S SRX SRX regi 2 5 - - STX STX regi 2 5 - - Notes: I affected - not affected Table 2.5. Arithmetic & Logic Instructions Set The computation al time required for each instruction consists of one clock pulse for each Cycle plus 3 clock pulses for the decoding phase. 19/99 ST52T301/E301 |
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