ST52T301 datasheet(41/100 Pages) STMICROELECTRONICS

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9 SERIAL COMMUNICATION INTERFACE

The Serial Communication Interfa ce (SCI)

integrated into the fuzzy processor ST52x301

provi des a gene ral p ur pose shift r egister

peripheral, that allows to link several widely

distributed MCUs, through their SCI subsystem.

The SCI gives a serial interfa ce providing

communication with common baud rates, up to

38400 Hz, and flexible character format.

The SCI is a full-duplex UART-type asynchronous

system with standard Non Return to Zero (NRZ)

format for the transmitted/received bit. The length

of the transmitted word is 10/11 bits (1 start bit, 8/9

data bits, 1 stop bit).

The SCI is composed of three modules: Receiver,

Transmitter and Baud-Rate Generator and it is

configured by means of Configuration Registers 3

and 1.

9.1 SCI RECEIVER BLOCK

T he SC I R ec ei ver block ma n ages t h e

synchronization of the serial data stream and

stores the data characters. The SCI Receiver is

mainly formed by two sub-systems: Recovery

Buffer Block and SCDR_RX Block.

The RE configuration bit set to ”1” (Configuration

The SCI receives data coming from the RxD pin

and drives the Recovery Buffer Block, that is a

high-speed shift register operating at a clock

frequency (CLOCK_RX) 16 times higher than the

fixed baud rate (CLOCK_TX). This sampling rate,

higher than the Baud Rate clock, allows to detect

Figure 9.1. SCI transmitted word structures

Figure 9.2. SCI Block Diagram

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ST52T301/E301

ST52T301 Datasheet(PDF) 41 Page - STMicroelectronics