AT80SND1C-ROTIL datasheet(108/210 Pages) ATMEL

108 / 210 page

108

AT8xC51SND1C

4109E–8051–06/03

Table 103. UFNUMH Register

UFNUMH (S:BBh, Read-only) – USB Frame Number High Register

Reset Value = 00h

Table 104. USBCLK Register

USBCLK (S:EAh) – USB Clock Divider Register

Reset Value = 0000 0000b

7654

3210

CRCOK

CRCERR

FNUM10

FNUM9

FNUM8

Bit

Number

Bit

Mnemonic

Description

7 - 3

Reserved

The value read from these bits is always 0. Do not set these bits.

5CRCOK

Frame Number CRC OK Bit

Set by hardware after a non corrupted Frame Number in Start of Frame Packet is

received.

Updated after every Start Of Frame packet reception.

Note: The Start Of Frame interrupt is generated just after the PID receipt.

CRCERR

Frame Number CRC Error Bit

Set by hardware after a corrupted Frame Number in Start of Frame Packet is

received.

Updated after every Start Of Frame packet reception.

Note: The Start Of Frame interrupt is generated just after the PID receipt.

Reserved

The value read from this bits is always 0. Do not set this bit.

2-0

FNUM10:8

Frame Number

Upper 3 bits of the 11-bit Frame Number. It is provided in the last received SOF

packet. FNUM does not change if a corrupted SOF is received.

7654

3210

------

USBCD1

USBCD0

Bit

Number

Bit

Mnemonic

Description

7 - 2

Reserved

The value read from these bits is always 0. Do not set these bits.

1 - 0

USBCD1:0

USB Controller Clock Divider

2-bit divider for USB controller clock generation.

AT80SND1C-ROTIL Datasheet(PDF) 108 Page - ATMEL Corporation

AT80SND1C-ROTIL Datasheet(HTML) 108 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL