AT80SND1C-ROTIL datasheet(114/210 Pages) ATMEL

114 / 210 page

114

AT8xC51SND1C

4109E–8051–06/03

required, to provide 8 (eight) clock cycles for the card to complete the operation

before shutting down the clock. Following is a list of the various bus transactions:

•

A command with no response. 8 clocks after the host command End bit.

•

A command with response. 8 clocks after the card command End bit.

•

A read data transaction. 8 clocks after the End bit of the last data block.

•

A write data transaction. 8 clocks after the CRC status token.

•

The host is allowed to shut down the clock of a “busy” card. The card will complete

the programming operation regardless of the host clock. However, the host must

provide a clock edge for the card to turn off its busy signal. Without a clock edge the

card (unless previously disconnected by a deselect command-CMD7) will force the

MDAT line down, forever.

Description

The MMC controller interfaces to the C51 core through the following eight special func-

tion registers:

MMCON0, MMCON1, MMCON2, the three MMC control registers (see Table 112 to

Table 120); MMSTA, the MMC status register (see Table 115); MMINT, the MMC inter-

rupt register (see Table 116); MMMSK, the MMC interrupt mask register (see

Table 117); MMCMD, the MMC command register (see Table 118); MMDAT, the MMC

data register (see Table 119); and MMCLK, the MMC clock register (see Table 120).

As shown in Figure 78, the MMC controller is divided in four blocks: the clock generator

that handles the MCLK (formally the MMC CLK) output to the card, the command line

controller that handles the MCMD (formally the MMC CMD) line traffic to or from the

card, the data line controller that handles the MDAT (formally the MMC DAT) line traffic

to or from the card, and the interrupt controller that handles the MMC controller interrupt

sources. These blocks are detailed in the following sections.

Figure 78. MMC Controller Block Diagram

Clock Generator

The MMC clock is generated by division of the oscillator clock (F

OSC) issued from the

Clock Controller block as detailed in Section "Oscillator", page 12. The division factor is

given by MMCD7:0 bits in MMCLK register, a value of 0x00 stops the MMC clock.

Figure 79 shows the MMC clock generator and its output clock calculation formula.

OSC

CLOCK

MCMD

MCLK

Internal

Bus

MDAT

Command Line

Clock

MMC

Interrupt

Request

Generator

Controller

Data Line

Controller

Interrupt

Controller

AT80SND1C-ROTIL Datasheet(PDF) 114 Page - ATMEL Corporation

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