7545 datasheet(34/62 Pages) RENESAS

34 / 62 page

Rev.1.06

Mar 07, 2008

Page 34 of 59

REJ03B0140-0106

7545 Group

Watchdog Timer

The watchdog timer gives a means for returning to a reset status

when the program fails to run on its normal loop due to a

runaway.

The watchdog timer consists of an 8-bit watchdog timer H and an

8-bit watchdog timer L, being a 16-bit counter.

1. Standard operation of watchdog timer

The watchdog timer is valid by setting “0” to bit 0 of the

Function set ROM data (address FFDA16) of the built-in

QzROM.

When an internal clock is supplied after waiting the oscillation

stabilizing time by timer 1 after system is released from reset, the

watchdog timer starts operation. When the watchdog timer H

underflows, an internal reset occurs. Accordingly, it is

programmed that the watchdog timer control register (address

003916) can be set before an underflow occurs.

When the watchdog timer control register (address 003916) is

read, the values of the high-order 6-bit of the watchdog timer H

and watchdog timer H count source selection bit are read.

2. Initial value of watchdog timer

By a reset or writing to the watchdog timer control register

(address 003916), the watchdog timer H is set to “FF16” and the

watchdog timer L is set to “FF16”.

3. Operation of watchdog timer H count source

selection bit

A watchdog timer H count source can be selected by bit 7 of the

watchdog timer control register (address 003916). When this bit

is “0”, the count source becomes a watchdog timer L underflow

signal. The detection time is 262.144 ms at f(XIN) = 4 MHz.

When this bit is “1”, the count source becomes f(XIN)/16. In this

case, the detection time is 1024

µs at f(XIN) = 4 MHz.

This bit is cleared to “0” after reset.

4. STP instruction function selection bit

The function of the STP instruction can be selected by the bit 1 in

FSROM. This bit cannot be used for rewriting by executing the

STP instruction.

• When this bit is set to “0”, internal reset occurs by executing

the STP instruction.

• When this bit is set to “1”, stop mode is entered by executing

the STP instruction.

1. The watchdog timer is operating during the wait mode.

Write data to the watchdog timer control register to prevent

timer underflow.

2. The watchdog timer stops during the stop mode. However,

the watchdog timer is running during the oscillation stabi-

lizing time after the STP instruction is released. In order to

avoid the underflow of the watchdog timer, the watchdog

timer H count source selection bit (bit 7 of watchdog timer

control register (address 003916)) must be set to “0” just

before executing the STP instruction.

Fig. 33 Structure of watchdog timer control register

Watchdog timer H (read only for high-order 6-bit)

Watchdog timer H count source selection bit

0 : Watchdog timer L underflow

1 : f(XIN)/16

Watchdog timer control register

(WDTCON: address 003916, initial value: 3F16)

Disable (returns “0” when read)

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