7545 datasheet(21/62 Pages) RENESAS

21 / 62 page

Rev.1.06

Mar 07, 2008

Page 21 of 59

REJ03B0140-0106

7545 Group

Fig. 16 Interrupt control diagram

• Interrupt Disable Flag

The interrupt disable flag is assigned to bit 2 of the processor

status register. This flag controls the acceptance of all interrupt

requests except for the BRK instruction. When this flag is set to

“1”, the acceptance of interrupt requests is disabled. When it is

set to “0”, acceptance of interrupt requests is enabled. This flag is

set to “1” with the SET instruction and set to “0” with the CLI

instruction.

When an interrupt request is accepted, the contents of the

processor status register are pushed onto the stack while the

interrupt disable flag remains set to “0”. Subsequently, this flag

is automatically set to “1” and multiple interrupts are disabled.

To use multiple interrupts, set this flag to “0” with the CLI

instruction within the interrupt processing routine.

The contents of the processor status register are popped off the

stack with the RTI instruction.

• Interrupt Request Bits

Once an interrupt request is generated, the corresponding

interrupt request bit is set to “1” and remains “1” until the request

is accepted . Wh en the reques t is accepted, th is bit is

automatically set to “0”.

Each interrupt request bit can be set to “0”, but cannot be set to

“1”, by software.

• Interrupt Enable Bits

The interrupt enable bits control the acceptance of the

corresponding interrupt requests. When an interrupt enable bit is

set to “0”, the acceptance of the corresponding interrupt request

is disabled. If an interrupt request occurs in this condition, the

corresponding interrupt request bit is set to “1”, but the interrupt

request is not accepted. When an interrupt enable bit is set to “1”,

acceptance of the corresponding interrupt request is enabled.

Each interrupt enable bit can be set to “0” or “1” by software.

The interrupt enable bit for an unused interrupt should be set to

“0”.

• Interrupt Edge Selection

The valid edge of external interrupt INT0 and INT1 can be

selected by the interrupt edge selection register(address003A16),

respectively.

• Key-on Wakeup Pin Selection

By setting the key-on wakeup pin selection register (address

001816), the valid or invalid of key-on wakeup for each pin can

be selected.

• Key-on Wakeup Edge Selection

By setting the key-on wakeup edge selection register (address

001916), the trigger edge of key-on wakeup for each pin can be

selected.

Interrupt disable flag I

Interrupt request

Interrupt request bit

Interrupt enable bit

BRK instruction

Reset

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