7545 datasheet(59/62 Pages) RENESAS

59 / 62 page

Rev.1.06

Mar 07, 2008

Page 59 of 59

REJ03B0140-0106

7545 Group

Notes on Oscillation Control

1. Stop mode

(1) When the stop mode is used, set “1” (STP instruction

enabled) to the STP instruction function selection bit (bit 1

of Function set ROM data (address FFDA16)).

(2) The oscillation stabilizing time after release of STP

instruction can be selected from “set automatically”/“not set

automatically” by the oscillation stabilizing time set bit after

release of the STP instruction (bit 0 of MISRG (address

3816)). When “0” is set to this bit, “0316” is set to timer 1

and “FF16” is set to prescaler 1 automatically at the

execution of the STP instruction. When “1” is set to this bit,

set the wait time to timer 1 and prescaler 1 according to the

oscillation stabilizing time of the oscillation. Also, when

timer 1 is used, set values again to timer 1 and prescaler 1

after system is returned from the stop mode.

Note on Power Source Voltage

When the power source voltage value of a microcomputer is less

than the value which is indicated as the recommended operating

conditions, the microcomputer does not operate normally and

may perform unstable operation.

In a system where the power source voltage drops slowly when

the power source voltage drops or the power supply is turned off,

reset a microcomputer when the supply voltage is less than the

recommended operating conditions and design a system not to

cause errors to the system by this unstable operation.

Note on Product Shipped in Blank

As for the product shipped in blank, Renesas does not perform

the writing test to user ROM area after the assembly process

though the QzROM writing test is performed enough before the

assembly process. Therefore, a writing error of approx.0.1 %

may occur.

Moreover, please note the contact of cables and foreign bodies

on a socket, etc. because a writing environment may cause some

writing errors.

Precautions Regarding Overvoltage

Make sure that voltage exceeding the VCC pin voltage is not

applied to other pins. In particular, ensure that the state indicated

by bold lines in Figure 7 does not occur for pin P40 (CNVSS

power source pin for QzROM) during power-on or power-off.

Otherwise the contents of QzROM could be rewritten.

Fig 7.

Example of Overvoltage

DATA REQUIRED FOR QzROM WRITING ORDERS

The following are necessary when ordering a QzROM product

shipped after writing:

1. QzROM Writing Confirmation Form*

2. Mark Specification Form*

3. ROM data...........Mask file

* For the QzROM writing confirmation form and the mark

specification form, refer to the “Renesas Technology Corp.”

Homepage (http://www.renesas.com/homepage.jsp).

Notes on QzROM Writing Orders

When ordering the QzROM product shipped after writing,

submit the mask file (extension: .msk) which is made by the

mask file converter MM.

Be sure to set the ROM option setup data (referred to as “Mask

option setup data” in MM) when making the mask file by using

the mask file converter MM.

Notes on ROM Code Protect

(QzROM product shipped after writing)

As for the QzROM product shipped after writing, the ROM code

protect is specified according to the ROM option setup data in

the mask file which is submitted at ordering.

Renesas Technology corp. write the value of the ROM option

setup data in the ROM code protect address (address FFDB16)

when writing to the QzROM. As a result, in the contents of the

ROM code protect address the ordered value may differ from the

actual written value.

The ROM option setup data in the mask file is “0016” for protect

enabled or “FF16” for protect disabled. Therefore, the contents of

the ROM code protect address of the QzROM product shipped

after writing is “0016” or “FF16”.

If you set except “0016” and “FF16” or nothing at the ROM

option data, we cannot generate the ROM data.

NOTES ON HARDWARE

Handling of Power Source Pin

In order to avoid a latch-up occurrence, connect a capacitor

suitable for high frequencies as bypass capacitor between power

source pin (VCC pin, VDDR pin) and GND pin (VSS pin). Besides,

connect the capacitor to as close as possible. For bypass

capacitor which should not be located too far from the pins to be

connected, a ceramic capacitor of 0.1

µF is recommended.

Handling of CNVSS Pin

The CNVSS pin is connected to the internal memory circuit block

by a low-ohmic resistance, since it has the multiplexed function

to be a programmable power source pin (VPP pin) as well.

To improve the noise reduction, make the length of wiring

between the CNVSS pin and the VSS pin the shortest possible.

VCC pin voltage

CNVSS pin voltage

“L” input

(1) Input voltage to other MCU pins rises before Vcc pin voltage.

(2) Input voltage to other MCU pins falls after Vcc pin voltage.

Note: The internal circuitry is unstable when Vcc is below the minimum voltage

specification of 1.8 V (shaded portion), so particular care should be

exercised regarding overvoltage.

1.8V

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