M38C89MB datasheet(41/55 Pages) RENESAS

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

38C8 Group

NOTES ON PROGRAMMING

Processor Status Register

The contents of the processor status register (PS) after a reset are

undefined, except for the interrupt disable flag (I) which is “1”. After a

reset, initialize flags which affect program execution. In particular, it

is essential to initialize the index X mode (T) and the decimal mode

(D) flags because of their effect on calculations.

Interrupts

The contents of the interrupt request bits do not change immediately

after they have been written. After writing to an interrupt request reg-

ister, execute at least one instruction before performing a BBC or

BBS instruction.

Decimal Calculations

• To calculate in decimal notation, set the decimal mode flag (D) to

“1”, then execute an ADC or SBC instruction. After executing an

ADC or SBC instruction, execute at least one instruction before

executing a SEC, CLC, or CLD instruction.

• In decimal mode, the values of the negative (N), overflow (V), and

zero (Z) flags are invalid.

Timers

If a value n (between 0 and 255) is written to a timer latch, the fre-

quency division ratio is 1/(n+1).

Multiplication and Division Instructions

• The index X mode (T) and the decimal mode (D) flags do not affect

the MUL and DIV instruction.

• The execution of these instructions does not change the contents

of the processor status register.

Ports

The contents of the port direction registers cannot be read. The fol-

lowing cannot be used:

• The data transfer instruction (LDA, etc.)

• The operation instruction when the index X mode flag (T) is “1”

• The addressing mode which uses the value of a direction register

as an index

• The bit-test instruction (BBC or BBS, etc.) to a direction register

• The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a

direction register.

Use instructions such as LDM and STA, etc., to set the port direction

registers.

Serial I/O

In clock synchronous serial I/O, if the receive side is using an exter-

nal clock and it is to output the SRDY signal, set the transmit enable

bit, the receive enable bit, and the SRDY output enable bit to “1”.

Serial I/O continues to output the final bit from the TxD pin after trans-

mission is completed.

A-D Converter

The comparator is constructed linked to a capacitor. When the con-

version speed is not enough, the conversion accuracy might be ru-

ined by the disappearance of the charge. When A-D conversion is

performed, set f(XIN) to at least 500 kHz.

When the following operations are performed, the A-D conversion

operation cannot be guaranteed.

•When the CPU mode register is operated during A-D conversion

operation,

•When the A-D control register is operated during A-D conversion

operation,

•When STP or WIT instruction is executed during A-D conversion

operation.

Instruction Execution Time

The instruction execution time is obtained by multiplying the frequency

of the internal clock

φ by the number of cycles needed to execute an

instruction.

The number of cycles required to execute an instruction is shown in

the list of machine instructions.

LCD Control

When using the voltage multiplier, apply prescribed voltage to the

VLIN pin in the state in which the LCD enable bit is “0”, and set the

voltage multiplier enable bit to “1”.

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