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M38C89MB Datasheet(PDF) 54 Page - Renesas Technology Corp

Part # M38C89MB
Description  SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PDF  55 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

M38C89MB Datasheet(HTML) 54 Page - Renesas Technology Corp

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REVISION HISTORY
38C8 GROUP DATA SHEET
Rev.
Date
Description
Page
Summary
(1/2)
1.0
01/18/01
First Edition
1.1
03/21/01
2
3
4
14
17
26
33
34
37
37
40
41
42
42
Figure 1 is partly revised.
Figure 2 is partly revised.
Pin name into Table 1 is partly revised.
Pin name into Table 5 is partly revised.
Explanations of “Interrupt Operation” are partly eliminated.
Address of [Baud Rate Generator (BRG)] is revised.
Figure name of Figure 31 is partly revised.
Figure name of Figure 32 is partly revised.
Explanations of “CLOCK GENERATING CIRCUIT” are partly revised.
Explanations of “(1) Middle-speed Mode” of “Frequency Control” are partly re-
vised.
“At STP Instruction Release” is eliminated.
Explanations of “DATA REQUIRED FOR MASK ORDERS” are partly revised.
Pin name of VIA into Table 11 is revised.
Limits of VIH, VIL of P40, P43 are revised.
1.2
10/15/01
3
15
16
41
42
43
43
43
43
43
46
46
47
Figure 2 is partly revised.
Figure 11 is partly revised.
Figure 12 is partly revised.
Table 10 is added.
Vcc parameter into Table 12 is partly eliminated.
Unit of f(CNTR0), f(CNTR1) into Table 13 is revised.
Limits of f(XIN) in high-speed mode (2.2 V
≤ Vcc < 4.0 V) into Table 13 is revised.
f(XIN) in middle-speed mode (2.2 V
≤ Vcc < 2.7 V) into Table 13 is added.
Unit of f(CNTR0), f(CNTR1) into Table 14 is revised.
f(XIN) in middle-speed mode (2.5 V
≤ Vcc < 2.7 V) into Table 14 is added.
Limits of tc(XIN), tWH(XIN), tWL(XIN) into Table 19 are added.
Limits and unit of tc(CNTR) into Table 19 are revised.
Table 20 is added.
1.3
12/05/01
3
14
17
18
28
28
28
40
Figure 2 is partly revised.
Table 5 is partly revised.
Explanations of “sNotes on interrupts” are partly revised.
Figure 14 is partly revised.
Explanations of “[A-D Control Register (ADCON)]” are partly revised.
Explanations of “Comparator and Control Circuit” are partly revised.
Figure 25 is partly revised.
Explanations of “A-D Converter” of “NOTES ON PROGRAMMING” are partly re-
vised.
1.4
06/25/02
All pages
1
3
4
6
8
9
10
11
14
Preliminary Notice in the header is eliminated.
Interrupts of “[FEATURES]” are corrected.
Figure 2 is partly revised.
Pin COM0–COM15 in Table 1 is revised.
Figure 4 is partly revised.
Note in Figure 4 is partly revised.
Explanations of bit 3 are added.
Bit 4 name in Figure 7 is revised.
Remarks in Figure 7 are partly revised.
Table 5 is partly revised.



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