HD6432147SW datasheet(162/1177 Pages) RENESAS

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Section 5 Interrupt Controller

Rev. 4.00 Sep 27, 2006 page 118 of 1130

REJ09B0327-0400

5.2.2

Interrupt Control Registers A to C (ICRA to ICRC)

ICR7

R/W

ICR6

R/W

ICR5

R/W

ICR4

R/W

ICR3

R/W

ICR0

R/W

ICR2

R/W

ICR1

R/W

Bit

Initial value

Read/Write

The ICR registers are three 8-bit readable/writable registers that set the interrupt control level for

interrupts other than NMI and address break.

The correspondence between ICR settings and interrupt sources is shown in table 5.3.

The ICR registers are initialized to H'00 by a reset and in hardware standby mode.

Bit n—Interrupt Control Level (ICRn): Sets the control level for the corresponding interrupt

source.

Bit n

ICRn

Description

Corresponding interrupt source is control level 0 (non-priority)

(Initial value)

Corresponding interrupt source is control level 1 (priority)

Note:

n = 7 to 0

Table 5.3

Correspondence between Interrupt Sources and ICR Settings

Bits

432

ICRA

IRQ0

IRQ1

IRQ2

IRQ3

IRQ4

IRQ5

IRQ6

IRQ7

DTC

Watchdog

timer 0

Watchdog

timer 1

ICRB

A/D

converter

Free-

running

timer

—

8-bit

timer

channel 0

8-bit

timer

channel 1

8-bit

timer

channels

X, Y

HIF,

Keyboard

buffer

controller

ICRC

SCI

channel 0

SCI

channel 1

SCI

channel 2

IIC

channel 0

(option)

IIC

channel 1

(option)

——

—

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