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HD6432147SW Datasheet(PDF) 180 Page - Renesas Technology Corp |
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HD6432147SW Datasheet(HTML) 180 Page - Renesas Technology Corp |
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180 / 1177 page ![]() Section 5 Interrupt Controller Rev. 4.00 Sep 27, 2006 page 136 of 1130 REJ09B0327-0400 Figure 5.7 shows a block diagram of the priority decision circuit. ICR UI I Default priority determination Vector number Interrupt acceptance control and 3-level mask control Interrupt source Interrupt control modes 0 and 1 Figure 5.7 Block Diagram of Interrupt Control Operation Interrupt Acceptance Control and 3-Level Control In interrupt control modes 0 and 1, interrupt acceptance control and 3-level mask control is performed by means of the I and UI bits in CCR, and ICR (control level). Table 5.6 shows the interrupts selected in each interrupt control mode. |
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