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SH7018 Datasheet(PDF) 71 Page - Renesas Technology Corp

Part # SH7018
Description  SuperH??RISC engine
PDF  431 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7018 Datasheet(HTML) 71 Page - Renesas Technology Corp

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5.5.1
Trap Instructions
When a TRAPA instruction is executed, trap instruction exception processing starts up. The CPU
operates as follows:
1. The status register (SR) is saved to the stack.
2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
instruction to be executed after the TRAPA instruction.
3. The exception service routine start address is fetched from the exception processing vector
table that corresponds to the vector number specified in the TRAPA instruction. That address
is jumped to and the program starts executing. The jump that occurs is not a delayed branch.
5.5.2
Illegal Slot Instructions
An instruction placed immediately after a delayed branch instruction is said to be placed in a delay
slot. When the instruction placed in the delay slot is undefined code, illegal slot exception
processing starts up when that undefined code is decoded. Illegal slot exception processing also
starts up when an instruction that rewrites the program counter (PC) is placed in a delay slot. The
processing starts when the instruction is decoded. The CPU handles an illegal slot instruction as
follows:
1. The status register (SR) is saved to the stack.
2. The program counter (PC) is saved to the stack. The PC value saved is the jump address of the
delayed branch instruction immediately before the undefined code or the instruction that
rewrites the PC.
3. The exception service routine start address is fetched from the exception processing vector
table that corresponds to the exception that occurred. That address is jumped to and the
program starts executing. The jump that occurs is not a delayed branch.
5.5.3
General Illegal Instructions
When undefined code placed anywhere other than immediately after a delayed branch instruction
(i.e., in a delay slot) is decoded, general illegal instruction exception processing starts up. The
CPU handles general illegal instructions the same as illegal slot instructions. Unlike processing of
illegal slot instructions, however, the program counter value stored is the start address of the
undefined code.



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