SH7018 datasheet(8/431 Pages) RENESAS

8 / 431 page

Section 5 Exception Processing ....................................................................................... 47

5.1

Overview............................................................................................................................ 47

5.1.1

Types of Exception Processing and Priority ........................................................ 47

5.1.2

Exception Processing Operations ......................................................................... 48

5.1.3

Exception Processing Vector Table...................................................................... 49

5.2

Resets................................................................................................................................. 51

5.2.1

Reset ..................................................................................................................... 51

5.2.2

Power-On Reset.................................................................................................... 51

5.3

Address Errors ................................................................................................................... 52

5.3.1

Address Error Exception Processing.................................................................... 52

5.4

Interrupts............................................................................................................................ 53

5.4.1

Interrupt Priority Level......................................................................................... 53

5.4.2

Interrupt Exception Processing ............................................................................ 54

5.5

Exceptions Triggered by Instructions................................................................................ 54

5.5.1

Trap Instructions .................................................................................................. 55

5.5.2

Illegal Slot Instructions ........................................................................................ 55

5.5.3

General Illegal Instructions .................................................................................. 55

5.6

When Exception Sources Are Not Accepted..................................................................... 56

5.6.1

Immediately after a Delayed Branch Instruction.................................................. 56

5.6.2

Immediately after an Interrupt-Disabled Instruction............................................ 56

5.7

Stack Status after Exception Processing Ends................................................................... 57

5.8

Notes on Use...................................................................................................................... 58

5.8.1

Value of Stack Pointer (SP).................................................................................. 58

5.8.2

Value of Vector Base Register (VBR) ................................................................. 58

5.8.3

Address Errors Caused by Stacking of Address Error Exception Processing...... 58

Section 6 Interrupt Controller (INTC) ........................................................................... 59

6.1

Overview............................................................................................................................ 59

6.1.1

Features ................................................................................................................ 59

6.1.2

Block Diagram...................................................................................................... 60

6.1.3

Pin Configuration ................................................................................................. 61

6.1.4

6.2

Interrupt Sources................................................................................................................ 62

6.2.1

NMI Interrupts...................................................................................................... 62

6.2.2

IRQ Interrupts ...................................................................................................... 62

6.2.3

On-Chip Peripheral Module Interrupts ................................................................ 63

6.2.4

Interrupt Exception Vectors and Priority Rankings ............................................. 63

6.3

Description of Registers .................................................................................................... 66

6.3.1

Interrupt Priority Registers A to H (IPRA to IPRH) ............................................ 66

6.3.2

Interrupt Control Register (ICR) .......................................................................... 67

6.3.3

IRQ Status Register (ISR) .................................................................................... 68

6.4

Interrupt Operation ............................................................................................................ 70

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