SH7018 datasheet(32/431 Pages) RENESAS

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Table 2.3

Delayed Branch Instructions

SH7018 CPU

Description

Example of Conventional CPU

BRA

TRGET

ADD

R1,R0

Executes an ADD before

branching to TRGET

ADD.W

R1,R0

BRA

TRGET

Multiplication/Accumulation Operation: 16-bit

× 16-bit → 32-bit multiplication operations are

executed in one to two cycles. 16-bit

× 16-bit + 64-bit → 64-bit multiplication/accumulation

operations are executed in two to three cycles. 32-bit

× 32-bit → 64-bit and 32-bit × 32-bit + 64-

bit

→ 64-bit multiplication/accumulation operations are executed in two to four cycles.

T Bit: The T bit in the status register changes according to the result of the comparison, and in

turn is the condition (true/false) that determines if the program will branch. The number of

instructions that change the T bit is kept to a minimum to improve the processing speed (table

2.4).

Table 2.4

T Bit

SH7018 CPU

Description

Example of Conventional CPU

CMP/GE

R1,R0

TRGET0

TRGET1

T bit is set when R0

≥ R1. The

program branches to TRGET0

when R0

≥ R1 and to TRGET1

when R0 < R1.

CMP.W

R1,R0

BGE

TRGET0

BLT

TRGET1

ADD

#1,R0

CMP/EQ

#0,R0

TRGET

T bit is not changed by ADD. T bit is

set when R0 = 0. The program

branches if R0 = 0.

SUB.W

#1,R0

BEQ

TRGET

Immediate Data: Byte (8-bit) immediate data resides in instruction code. Word or longword

immediate data is not input via instruction codes but is stored in a memory table. An immediate

data transfer instruction (MOV) accesses the memory table using the PC relative addressing mode

with displacement (table 2.5).

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