SH7018 datasheet(9/431 Pages) RENESAS

9 / 431 page

iii

6.4.1

Interrupt Sequence................................................................................................ 70

6.4.2

Stack after Interrupt Exception Processing .......................................................... 72

6.5

Interrupt Response Time.................................................................................................... 72

Section 7 Bus State Controller (BSC)............................................................................ 75

7.1

Overview............................................................................................................................ 75

7.1.1

Features ................................................................................................................ 75

7.1.2

Block Diagram...................................................................................................... 76

7.1.3

Pin Configuration ................................................................................................. 77

7.1.4

7.1.5

Address Map ........................................................................................................ 78

7.2

Description of Registers .................................................................................................... 80

7.2.1

Bus Control Register 1 (BCR1)............................................................................ 80

7.2.2

Bus Control Register 2 (BCR2)............................................................................ 82

7.2.3

Wait Control Register 1 (WCR1) ......................................................................... 86

7.3

Accessing Ordinary Space ................................................................................................. 88

7.3.1

Basic Timing ........................................................................................................ 88

7.3.2

Wait State Control ................................................................................................ 89

7.3.3

CS Assert Period Extension.................................................................................. 91

7.4

Waits between Access Cycles ........................................................................................... 92

7.4.1

Prevention of Data Bus Conflicts ......................................................................... 92

7.4.2

Simplification of Bus Cycle Start Detection ........................................................ 93

7.5

Memory Connection Examples ......................................................................................... 94

Section 8 Multifunction Timer Pulse Unit (MTU) .................................................... 95

8.1

Overview............................................................................................................................ 95

8.1.1

Features ................................................................................................................ 95

8.1.2

Block Diagram...................................................................................................... 98

8.1.3

Pin Configuration ................................................................................................. 99

8.1.4

8.2

MTU Register Descriptions ............................................................................................... 101

8.2.1

Timer Control Register (TCR) ............................................................................. 101

8.2.2

Timer Mode Register (TMDR) ............................................................................ 105

8.2.3

Timer I/O Control Register (TIOR) ..................................................................... 106

8.2.4

Timer Interrupt Enable Register (TIER) .............................................................. 114

8.2.5

Timer Status Register (TSR) ................................................................................ 116

8.2.6

Timer Counters (TCNT)....................................................................................... 118

8.2.7

Timer General Register (TGR) ............................................................................ 119

8.2.8

Timer Start Register (TSTR)................................................................................ 119

8.2.9

Timer Synchro Register (TSYR).......................................................................... 120

8.3

Bus Master Interface.......................................................................................................... 121

8.3.1

16-Bit Registers.................................................................................................... 121

8.3.2

8-Bit Registers...................................................................................................... 121

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