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MPC8272EC Datasheet(PDF) 34 Page - Freescale Semiconductor, Inc |
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MPC8272EC Datasheet(HTML) 34 Page - Freescale Semiconductor, Inc |
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34 / 60 page ![]() MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 34 Freescale Semiconductor Clock Configuration Modes 1110_001 50.0 100.0 3 150.0 300.0 4 200.0 400.0 6 25.0 50.0 1110_010 50.0 100.0 3 150.0 300.0 4.5 225.0 450.0 6 25.0 50.0 1110_011 50.0 100.0 3 150.0 300.0 5 250.0 500.0 6 25.0 50.0 1110_100 50.0 100.0 3 150.0 300.0 5.5 275.0 550.0 6 25.0 50.0 1100_000 Reserved 1100_001 Reserved 1100_010 Reserved 1 The “low” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency in a table entry guarantees only the required minimum CPU operating frequency. The “high” values are for the purpose of illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed the frequency rating of the user’s device. The minimum CPU frequency is 150 MHz for commercial temperature devices and 175 MHz for extended temperature devices. The minimum CPM frequency is 120 MHz. 2 PCI_MODCK determines the PCI clock frequency range. Refer to Table 16 for higher range configurations. 3 MODCK_H = hard reset configuration word [28–31] (refer to Section 5.4 in the MPC8260 User’s Manual). MODCK[1-3] = three hardware configuration pins. 4 CPM multiplication factor = CPM clock/bus clock 5 CPU multiplication factor = Core PLL multiplication factor 6 CPM_CLK/PCI_CLK ratio. When PCI_MODCK = 1, the ratio of CPM_CLK/PCI_CLK should be calculated from PCIDF as follows: PCIDF = 3 > CPM_CLK/PCI_CLK = 4 PCIDF = 5 > CPM_CLK/PCI_CLK = 6 PCIDF = 7 > CPM_CLK/PCI_CLK = 8 PCIDF = 9 > CPM_CLK/PCI_CLK = 5 PCIDF = B > CPM_CLK/PCI_CLK = 6 Table 17. Clock Configurations for PCI Host Mode (PCI_MODCK=1) 1, 2 (continued) Mode 3 Bus Clock (MHz) CPM Multiplication Factor 4 CPM Clock (MHz) CPU Multiplication Factor 5 CPU Clock (MHz) PCI Division Factor 6 PCI Clock (MHz) MODCK_H- MODCK[1-3] Low High Low High Low High Low High |
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