MPC8610EC datasheet(39/96 Pages) FREESCALE

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Electrical Characteristics

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0

Freescale Semiconductor

Figure 13 depicts the vertical timing (timing of one frame), including both the vertical sync pulse and the data. All parameters

shown in the diagram are programmable.

Figure 13. TFT DIU/LCD Interface Timing Diagram—Vertical Sync Pulse

Table 28 shows timing parameters of signals presented in Figure 12 and Figure 13.

Table 28. DIU Interface AC Timing Parameters—Pixel Level

Parameter

Symbol

Value

Unit

Notes

Display pixel clock period

tPCP

7.5 (minimum)

1, 2

1 Display interface pixel clock period immediate value (in nanoseconds).

2 Display pixel clock frequency must also be less than or equal to 1/3 the platform clock.

HSYNC width

tPWH

PW_H

× tPCP

HSYNC back porch width

tBPH

BP_H

× tPCP

HSYNC front porch width

tFPH

FP_H

× tPCP

Screen width

tSW

DELTA_X

× tPCP

HSYNC (line) period

tHSP

(PW_H + BP_H + DELTA_X + FP_H)

× tPCP

VSYNC width

tPWV

PW_V

× tHSP

HSYNC back porch width

tBPV

BP_V

× tHSP

HSYNC front porch width

tFPV

FP_V

× tHSP

Screen height

tSH

DELTA_Y

× tHSP

VSYNC (frame) period

tVSP

(PW_V + BP_V + DELTA_Y + FP_H)

× tHSP

Notes:

DELTA_Y

Tpwv

Tbpv

Tsh

Tfpv

DIU_HSYNC

DIU_LD

DIU_VSYNC

DIU_DE

Thsp

(Line Data)

Start of Frame

Invalid Data

Tvsp

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