EPLD datasheet(6/42 Pages) ALTERA

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Altera Corporation

Classic EPLD Family Data Sheet

EP610, EP610I, EP910, and EP910I devices have a global feedback

conﬁguration; either the macrocell output (Q) or the I/O pin input (I/O)

can feed back to the AND array so that it is accessible to all other

macrocells.

EP1810 macrocells can have either of two feedback configurations:

quadrant or dual. Most macrocells in EP1810 devices have a quadrant

feedback configuration; either the macrocell output or I/O pin input can

feed back to other macrocells in the same quadrant. Selected macrocells in

EP1810 devices have a dual feedback configuration: the output of the

macrocell feeds back to other macrocells in the same quadrant, and the

I/O pin input feeds back to all macrocells in the device. If the associated

I/O pin is not used, the macrocell output can optionally feed all

macrocells in the device. In this case, the output of the macrocell passes

through the tri-state buffer and uses the feedback path between the buffer

and the I/O pin.

Design Security

Classic devices contain a programmable security bit that controls access to

the data programmed into the device. When this bit is programmed, a

proprietary design implemented in the device cannot be copied or

retrieved. This feature provides a high level of design security because

data within configuration elements is invisible. The security bit that

controls this function and other program data is reset only when the

device is erased.

Timing Model

Device timing can be analyzed with the MAX+PLUS II software, with a

variety of popular industry-standard EDA simulators and timing

analyzers, or with the timing model shown in Figure 4. Devices have fixed

internal delays that allow the user to determine the worst-case timing for

any design. The MAX+PLUS II software provides timing simulation,

point-to-point delay prediction, and detailed timing analysis for system-

level performance evaluation.

Figure 4. Classic Timing Model

I/O

Delay

tIO

Feedback

Delay

tFD

Output

Delay

tOD

tXZ

tZX

Input

Delay

tIN

Logic Array

Delay

tLAD

tCLR

Array Clock

Delay

tIC

tSU

tICS

Global Clock

Delay

EPLD Datasheet(PDF) 6 Page - Altera Corporation

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