EPLD datasheet(9/42 Pages) ALTERA

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Altera Corporation

753

Classic EPLD Family Data Sheet

Turbo Bit

Option

Many Classic devices contain a programmable Turbo BitTM option to

control the automatic power-down feature that enables the low-standby-

power mode. When the Turbo Bit option is turned on, the low-standby-

power mode is disabled. All AC values are tested with the Turbo Bit

option turned on. When the device is operating with the Turbo Bit option

turned off (non-Turbo mode), a non-Turbo adder must be added to the

appropriate AC parameter to determine worst-case timing. The non-

Turbo adder is specified in the “AC Operating Conditions” tables for each

Classic device that supports the Turbo mode.

Generic Testing

Classic devices are fully functionally tested. Complete testing of each

programmable EPROM configuration element and all internal logic

elements before and after packaging ensures 100% programming yield.

See Figure 6 for AC test measurement conditions. These devices also

contain on-board logic test circuitry to allow veriﬁcation of function and

AC speciﬁcations during standard production ﬂow.

Figure 6. AC Test Conditions

Device

Programming

Classic devices can be programmed on 486- and Pentium-based PCs with

the MAX+PLUS II Programmer, an Altera Logic Programmer card, the

MPU, and the appropriate device adapter. The MPU performs continuity

checking to ensure adequate electrical contact between the adapter and

the device.

Data I/O, BP Microsystems, and other programming hardware

manufacturers also offer programming support for Altera devices. See

Programming Hardware Manufacturers for more information.

VCC

To Test

System

C1 (includes

JIG capacitance)

885

Ω

Device

Output

340

Ω

Power-supply transients can affect AC

measurements. Simultaneous transitions of

multiple outputs should be avoided for

accurate measurement. Threshold tests

must not be performed under AC

conditions. Large-amplitude, fast ground-

current transients normally occur as the

device outputs discharge the load

capacitances. When these transients ﬂow

through the parasitic inductance between

the device ground pin and the test system

ground, signiﬁcant reductions in observable

noise immunity can result.

EPLD Datasheet(PDF) 9 Page - Altera Corporation

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