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EPLD Datasheet(PDF) 8 Page - Altera Corporation

Part # EPLD
Description  The Altera Classic device family offers a solution to high-speed, lowpower logic integration. Fabricated on advanced CMOS technology
PDF  42 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EPLD Datasheet(HTML) 8 Page - Altera Corporation

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752
Altera Corporation
Classic EPLD Family Data Sheet
Figure 5. Classic Switching Waveforms
I/O Pin
Input Pin
Logic Array Input
Logic Array Output
Output Pin
tIN
tLAD
tCLR
tOD
tIO
Input Mode
tPD1 = tIN + tLAD + tOD
tPD2 = tIO + tIN + tLAD + tOD
tFD
tASU
Clock Pin
Clock into Logic Array
Clock from Logic Array
Data from Logic Array
Register Output to Logic Array
tR
tACH
tIN
t
F
tIC
tACL
tAH
Array Clock Mode
Global Clock Pin
Global Clock at Register
Data from Logic Array
tR
tIN
tICS
tSU
tH
tF
tCH
tCL
Global Clock Mode
tOD
Clock from Logic Array
Data from Logic Array
Output Pin
High-Impedance
Tri-State
tZX
tXZ
Output Mode
tR and tF < 3 ns.
Inputs are driven at 3 V
for a logic high and
0 V for a logic low.
All timing characteristics
are measured at 1.5 V.



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