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EPLD Datasheet(PDF) 20 Page - Altera Corporation

Part # EPLD
Description  The Altera Classic device family offers a solution to high-speed, lowpower logic integration. Fabricated on advanced CMOS technology
PDF  42 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EPLD Datasheet(HTML) 20 Page - Altera Corporation

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Altera Corporation
Classic EPLD Family Data Sheet
Tables 12 and 13 show the timing parameters for EP610I devices.
Table 12. EP610I External Timing Parameters
Notes (1), (2)
Symbol
Parameter
Conditions EP610I-10 EP610I-12 EP610I-15
Non-Turbo
Adder
Unit
Min Max Min Max Min Max
(3)
tPD1
Input to non-registered output
C1 = 35 pF
10.0
12.0
15.0
25.0
ns
tPD2
I/O input to non-registered output
10.0
12.0
15.0
25.0
ns
tPZX
Input to output enable
15.0
15.0
18.0
25.0
ns
tPXZ
Input to output disable
C1 = 5 pF
(4)
13.0
15.0
18.0
25.0
ns
tCLR
Asynchronous output clear time
C1 = 35 pF
13.0
15.0
18.0
25.0
ns
fMAX
Maximum frequency
(5)
125.0
100.
0
83.3
0.0
MHz
tSU
Global clock input setup time
7.0
9.0
12.0
25
ns
tH
Global clock input hold time
0.0
0.0
0.0
0.0
ns
tCH
Global clock high time
5.0
5.0
5.0
0.0
ns
tCL
Global clock low time
5.0
5.0
5.0
0.0
ns
tCO1
Global clock to output delay
6.5
8.0
8.0
0.0
ns
tCNT
Global clock minimum period
10.0
12.0
15.0
25.0
ns
fCNT
Maximum internal global clock
frequency
(6)
100.0
83.3
66.0
0.0
MHz
tASU
Array clock input setup time
1.5
3.0
4.0
25.0
ns
tAH
Array clock input hold time
5.5
6.0
6.0
0.0
ns
tACH
Array clock high time
5.0
5.0
6.0
0.0
ns
tACL
Array clock low time
5.0
5.0
6.0
0.0
ns
tODH
Output data hold time after clock
C1 = 35 pF
(7)
1.0
1.0
1.0
ns
tACO1
Array clock to output delay
12.0
14.0
16.0
25.0
ns
tACNT
Array clock minimum period
10.0
12.0
15.0
25.0
ns
fACNT
Maximum internal array clock
frequency
(6)
100.0
83.3
66.0
0.0
MHz



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