EPLD datasheet(24/42 Pages) ALTERA

24 / 42 page

768

Altera Corporation

Classic EPLD Family Data Sheet

General

Description

Altera EP910 devices can implement up to 450 usable gates of SSI and MSI

logic functions. EP910 devices have 24 macrocells, 12 dedicated input

pins, 24 I/O pins, and 2 global clock pins (see Figure 12). Each macrocell

can access signals from the global bus, which consists of the true and

complement forms of the dedicated inputs and the true and complement

forms of either the output of the macrocell or the I/O input. The CLK1 and

CLK2

signals are the dedicated clock inputs for the registers in macrocells

13 through 24 and 1 through 12, respectively.

Figure 12. EP910 Block Diagram

Numbers without parentheses are for DIP packages. Numbers in parentheses are for J-lead packages.

(40)

(38)

(37)

(36)

(35)

(34)

(33)

(32)

(31)

(30)

(29)

(28)

(6)

(7)

(8)

(9)

(10)

(11)

(12)

(13)

(14)

(15)

(16)

(18)

Macrocell 13

Macrocell 14

Macrocell 15

Macrocell 16

Macrocell 17

Macrocell 18

Macrocell 19

Macrocell 20

Macrocell 21

Macrocell 22

Macrocell 23

Macrocell 24

Macrocell 1

Macrocell 2

Macrocell 3

Macrocell 4

Macrocell 5

Macrocell 6

Macrocell 7

Macrocell 8

Macrocell 9

Macrocell 10

Macrocell 11

Macrocell 12

(3)

(4)

(5)

(2)

INPUT

CLK1

(19)

(20)

(21)

INPUT

CLK2

Global

Bus

(27)

(26)

(25)

INPUT

(43)

(42)

(41)

(24)

EPLD Datasheet(PDF) 24 Page - Altera Corporation

EPLD Datasheet(HTML) 24 Page - Altera Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

Datasheet Download

Link URL