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ATA5429-PLSW Datasheet(PDF) 65 Page - ATMEL Corporation |
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ATA5429-PLSW Datasheet(HTML) 65 Page - ATMEL Corporation |
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65 / 100 page ![]() 65 4841D–WIRE–10/07 ATA5423/ATA5425/ATA5428/ATA5429 9.3 Interrupts Via pin IRQ, the transceiver signals different operating conditions to a connected microcontrol- ler. If a specific operating condition occurs, pin IRQ is set to high. If an interrupt occurs, it is recommended to delete the interrupt immediately by reading the sta- tus register, so that a further potential interrupt doesn’t get lost. If the Interrupt pin doesn’t switch to low by reading the status register, the interrupt was triggered by the RX/TX data buffer. In this case read or write the RX/TX data buffer according to Table 9-6. Table 9-5. TX Modulation Schemes Mode ASK/_NFSK P_Mode T_Mode Bit in TX/RX Data Buffer Level on Pin SDI_TMDI RFOUT TX 0 001 X fFSK_L → fFSK_H 000 X fFSK_H → fFSK_L 101 X fFSK_H 100 X fFSK_L X1X 1 fFSK_H X1X 0 fFSK_L 1 001 X fASK off → fASK on 000 X fASK on → fASK off 101 X fASK on 100 X fASK off X1X 1 fASK on X1X 0 fASK off Table 9-6. Interrupt Handling Operating Conditions Which Set Pin IRQ to High Level Operations Which Set Pin IRQ to Low Level Events in Status Register State transition of status bit STn (0 → 1; 1 → 0) Read status register or Command Delete IRQ Appearance of status bit Power_On (0 → 1) Appearance of status bit P_On_Aux (0 → 1) Events During TX Operation (T_MODE = 0) 4, 8 or 12 Bytes are in the TX data buffer or the TX data buffer is empty (depends on IR0 and IR1 in control register 1). Write TX data buffer or Write control register 1 or Write control register 4 or Write control register 5 or Write control register 6 or Command delete IRQ Events During RX Operation (T_MODE = 0) 4, 8 or 12 received bytes are in the RX data buffer or a receiving error is occurred (depends on IR0 and IR1 in control register 1). Read RX data buffer(1) or Write control register 1 or Write control register 4 or Write control register 5 or Write control register 6 or Command delete IRQ Successful bit check (P_MODE = 0) Note: 1. During reading of the RX/TX buffer, no IRQ is issued, due to the received bytes or a receiving error. |
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