ATA5429-PLSW datasheet(43/100 Pages) ATMEL

43 / 100 page

4841D–WIRE–10/07

ATA5423/ATA5425/ATA5428/ATA5429

7.4

Status Register

The status register indicates the current status of the transceiver and is readable via the 4-wire

serial interface. Setting Power_On or P_On_Aux or an event on ST1, ST2, ST3, ST4 or ST5 is

indicated by an IRQ.

Reading the status register resets the bits Power_On, Low_Batt, P_On_Aux and the IRQ.

7.4.1

Status Register (ADR 8)

Table 7-21.

Control Register 6 (Function of Bit 5, Bit 4, Bit 3, Bit 2, Bit 1 and Bit 0)

Lim_max5

Lim_max4

Lim_max3

Lim_max2

Lim_max1

Lim_max0

Function Lim_max

(Lim_max < 12 is not Applicable)

(TLim_max = (Lim_max – 1) × TXDCLK)

0110

....

1110

Lim_max = (28 – 1) × TXDCLK)

(default)

....

1111

Table 7-22.

Status Register

Status Bit

Function

ST5

Status of pin T5

Pin T5 = 0

→ ST5 = 1

Pin T5 = 1

→ ST5 = 0

(see Figure 7-3 on page 45)

ST4

Status of pin T4

Pin T4 = 0

→ ST4 = 1

Pin T4 = 1

→ ST4 = 0

(see Figure 7-3 on page 45)

ST3

Status of pin T3

Pin T3 = 0

→ ST3 = 1

Pin T3 = 1

→ ST3 = 0

(see Figure 7-3 on page 45)

ST2

Status of pin T2

Pin T2 = 0

→ ST2 = 1

Pin T2 = 1

→ ST2 = 0

(see Figure 7-3 on page 45)

ST1

Status of pin T1

Pin T1 = 0

→ ST1 = 1

Pin T1 = 1

→ ST1 = 0

(see Figure 7-3 on page 45)

ATA5429-PLSW Datasheet(PDF) 43 Page - ATMEL Corporation

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