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ATA5429-PLSW Datasheet(PDF) 34 Page - ATMEL Corporation

Part # ATA5429-PLSW
Description  UHF ASK/FSK Transceiver
PDF  100 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

ATA5429-PLSW Datasheet(HTML) 34 Page - ATMEL Corporation

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34
4841D–WIRE–10/07
ATA5423/ATA5425/ATA5428/ATA5429
The status bit Low_Batt is set to “1” if the voltage at pin VSOUT V
VSOUT drops below VThres_2
(typically 2.38V). Low_Batt is set to “0” if V
VSOUT exceeds VThres_2 and the status register is read
via the 4-wire serial interface or N_RESET is set to low.
If V
VSOUT drops below VThres_1 (typically 2.3V), N_RESET is set to low. If bit VSOUT_EN in con-
trol register 3 is “1”, a DVCC_RESET is also generated. If V
VSOUT was already disabled by the
connected microcontroller by setting bit VSOUT_EN = 0, no DVCC_RESET is generated.
Note:
If VSOUT < V
Thres_1 (typically 2.3 V) the output of the pin CLK is low, the Microcontroller_Interface
is disabled and the transceiver is not programmable via the 4-wire serial interface.
Figure 5-3.
Reset Timing
N_RESET
VSOUT_EN
(Control Register 3)
LOW_Batt
(Status Register)
DVCC_RESET
VSOUT
VSOUT
DVCC
(AVCC)
V
Thres_1 = 2.3V (typ)
1.5V (typically)
V
Thres_2 = 2.38V (typ)
V
SOUT > 2.3V and the XTO is running
V
SOUT > 2.38V and the XTO is running



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