ATA5429-PLSW datasheet(42/100 Pages) ATMEL

42 / 100 page

4841D–WIRE–10/07

ATA5423/ATA5425/ATA5428/ATA5429

7.3.6

Control Register 6 (ADR 5)

Table 7-18.

Control Register 5 (Function of Bit 5, Bit 4, Bit 3, Bit 2, Bit 1 and Bit 0 in RX Mode)

Lim_min5

Lim_min4

Lim_min3

Lim_min2

Lim_min1

Lim_min0

Function (RX Mode)

Lim_min

(Lim_min < 10 are not applicable)

(TLim_min = Lim_min × TXDCLK)

...

Lim_min = 16 × TXDCLK)

(default)

...

Table 7-19.

Control Register 5 (Function of Bit 5, Bit 4, Bit 3, Bit 2, Bit 1 and Bit 0 in TX Mode)

Lim_min5

Lim_min4

Lim_min3

Lim_min2

Lim_min1

Lim_min0

Function (TX Mode) Lim_min

(Lim_min < 10 are not applicable)

(TX_Bitrate = 1/((Lim_min + 1)

× T

XDCLK × 2)

001

010

001

011

...

010

000

(TX_Bitrate = 1/((16 + 1)

× T

XDCLK × 2)

(default)

...

111

Table 7-20.

Control Register 6 (Function of Bit 7 and Bit 6)

Baud1

Baud0

Function

Bit

-rate range 0 (B0) 1.0 Kbit/s to 2.5 Kbit/s;

TXDCLK = 8 × TDCLK × XLim

Bit

-rate range 1 (B1) 2.0 Kbit/s to 5.0 Kbit/s;

XDCLK = 4 × TDCLK × XLim

Bit

-rate range 2 (B2) 4.0 Kbit/s to 10.0 Kbit/s;

TXDCLK = 2 × TDCLK × XLim; (default)

Bit

-rate range 3 (B3) 8.0 Kbit/s to 20.0 Kbit/s;

TXDCLK = 1 × TDCLK × XLim

Note that the receiver does not work with >10 Kbit/s in ASK mode

ATA5429-PLSW Datasheet(PDF) 42 Page - ATMEL Corporation

ATA5429-PLSW Datasheet(HTML) 42 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

Datasheet Download

Link URL