ATA6842-PLSW datasheet(20/29 Pages) ATMEL

20 / 29 page

4964B–AUTO–07/07

ATA6842

7.9

Watchdog

The open loop watchdog (window comparator) compares each time interval between a falling

and a rising edge with a given reference time interval. The lower window time is between

× t

WD and 91 × tWD and the upper window time is between 122 × tWD and 123 × tWD

WD =2/fOSC). The watchdog includes an error counter WDC(2:0) which is incremented by one

when there are valid trigger events and decremented by three when there are watchdog errors.

If the counter reaches a value of zero (state S0: 000), the warning lamp will be switched on.

Relay drivers, TCFET-, low- and high-side drivers are disabled. With a counter value greater

than or equal to seven (state S7: 111), the watchdog stops affecting the drivers. In the case of a

watchdog timeout (322

× t

WD to 323 × tWD), the error counter is immediately set to zero. The ini-

tial state of the watchdog counter after power-up or if RESN is low is 110 (state S6). The

watchdog can be reset by RSTN.

Figure 7-1.

State Diagram

000

001

101

110

111

100

011

010

bad | timeout

timeout

good

bad

good

timeout

ATA6842-PLSW Datasheet(PDF) 20 Page - ATMEL Corporation