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AX2000-1CS896M Datasheet(PDF) 102 Page - Actel Corporation |
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AX2000-1CS896M Datasheet(HTML) 102 Page - Actel Corporation |
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102 / 226 page  Axcelerator Family FPGAs 2- 88 v2.7 Table 2-100 • Eight FIFO Blocks Cascaded Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70°C '–2' Speed '–1' Speed 'Std' Speed Parameter Description Min. Max. Min. Max. Min. Max. Units FIFO Module Timing tWSU Write Setup 5.78 6.58 7.74 ns tWHD Write Hold 0.22 0.25 0.3 ns tWCKH WCLK High 0.98 1.11 1.31 ns tWCKL WCLK Low 6.68 7.6 8.94 ns tWCKP Minimum WCLK Period 13.36 15.2 17.88 ns tRSU Read Setup 6.75 7.69 9.04 ns tRHD Read Hold 0 0 0 ns tRCKH RCLK High 0.95 1.08 1.27 ns tRCKL RCLK Low 7.51 8.55 10.05 ns tRCKP Minimum RCLK period 15.02 17.1 20.1 ns tCLRHF Clear High 1.08 1.23 1.45 ns tCLR2FF Clear-to-flag (EMPTY/FULL) 2.02 2.3 2.7 ns tCLR2AF Clear-to-flag (AEMPTY/AFULL) 4.62 5.26 6.19 ns tCK2FF Clock-to-flag (EMPTY/FULL) 2.24 2.55 3 ns tCK2AF Clock-to-flag (AEMPTY/AFULL) 5.31 6.05 7.11 ns tRCK2RD1 RCLK-To-OUT (Pipelined) 3.57 4.06 4.77 ns tRCK2RD2 RCLK-To-OUT (Nonpipelined) 5.48 6.24 7.34 ns Table 2-101 • Sixteen FIFO Blocks Cascaded Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70°C '–2' Speed '–1' Speed 'Std' Speed Parameter Description Min. Max. Min. Max. Min. Max. Units FIFO Module Timing tWSU Write Setup 16.54 18.84 22.15 ns tWHD Write Hold 0.22 0.25 0.3 ns tWCKH WCLK High 0.98 1.11 1.31 ns tWCKL WCLK Low 17.44 19.86 23.35 ns tWCKP Minimum WCLK Period 34.88 39.72 46.7 ns tRSU Read Setup 18.13 20.65 24.27 ns tRHD Read Hold 0 0 0 ns tRCKH RCLK High 0.95 1.08 1.27 ns tRCKL RCLK Low 18.75 21.36 25.11 ns tRCKP Minimum RCLK period 37.5 42.72 50.22 ns tCLRHF Clear High 1.08 1.23 1.45 ns tCLR2FF Clear-to-flag (EMPTY/FULL) 2.02 2.3 2.7 ns tCLR2AF Clear-to-flag (AEMPTY/AFULL) 4.62 5.26 6.19 ns tCK2FF Clock-to-flag (EMPTY/FULL) 2.24 2.55 3 ns tCK2AF Clock-to-flag (AEMPTY/AFULL) 5.31 6.05 7.11 ns tRCK2RD1 RCLK-To-OUT (Pipelined) 12.71 14.48 17.03 ns tRCK2RD2 RCLK-To-OUT (Nonpipelined) 13.91 15.85 18.63 ns |
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