AX2000-1CS896M datasheet(104/226 Pages) ACTEL

104 / 226 page

Axcelerator Family FPGAs

2- 90

v2.7

Instruction Register (IR) and the Data Registers (such as

BSR,

IDCODE,

USRCODE,

BYPASS,

etc.).

The

TAP

Controller steps into one of the states depending on the

sequence of TMS at the rising edges of TCK.

Instruction Register (IR)

The IR has five bits (IR4 to IR0). At the TRST state, IR is

reset to IDCODE. Each time when IR is selected, it goes

through "select IR-Scan," "Capture-IR," "Shift-IR," all the

way through "Update-IR." When there is no test error,

the first five data bits coming out of TDO during the

"Shift-IR" will be "10111." If a test error occurs, the last

three bits will contain one to three zeroes corresponding

negatively

asserted

signals:

"TDO_ERRORB,"

"PROBA_ERRORB," and "PROBB_ERRORB." The error(s)

will be erased when the TAP is at the "Update-IR" or the

TRST state. When in user mode start-up sequence, if the

micro-probe has not been used, the "PROBA_ERRORB" is

used as a "Power-up done successfully" flag.

Data Registers (DRs)

Data registers are distributed throughout the chip. They

store testing/programming vectors. The MSB of a data

to TDO. There are different types of data registers.

Descriptions of the main registers are as follow:

1. IDCODE:

The IDCODE is a 33-bit hard coded JTAG Silicon

Signature. It is a hardwired device ID code, which

contains the Actel identity, part number, and version

number in a specific JTAG format.

2. USERCODE:

The USERCODE is a 32-bit programmable JTAG Silicon

Signature. It is a supplementary identity code for the

user to program information to distinguish different

programmed parts. USERCODE fuses will read out as

"zeroes" when not programmed, so only the "1" bits

need to be programmed.

3. Boundary-Scan Register (BSR):

Each I/O contains three Boundary-Scan Cells. Each cell

has a shift register bit, a latch, and two MUXes. The

boundary-scan cells are used for the Output-enable

(E), Output (O), and Input (I) registers. The bit order

of the boundary-scan cells for each of them is E-O-I.

The boundary-scan cells are then chained serially to

form the Boundary-Scan Register (BSR). The length of

the BSR is the number of I/Os in the die multiplied by

three.

4. Bypass Register (BYR):

This is the "1-bit" register. It is used to shorten the

TDI-TDO serial chain in board-level testing to only

one bit per device not being tested. It is also selected

for all "reserved" or unused instructions.

Probing

Internal activities of the JTAG interface can be observed

via the Silicon Explorer II probes: "PRA," "PRB," "PRC,"

and "PRD."

Special Fuses

Security

Actel antifuse FPGAs, with FuseLock technology, offer

the highest level of design security available in a

programmable logic device. Since antifuse FPGAs are

live-at power-up, there is no bitstream that can be

intercepted, and no bitstream or programming data is

ever downloaded to the device during power-up, thus

making device cloning impossible.

In addition, special

security fuses are hidden throughout the fabric of the

device and may be programmed by the user to thwart

attempts to reverse engineer the device by attempting

to exploit either the programming or probing interfaces.

Both invasive and noninvasive attacks against an

Axcelerator device that access or bypass these security

fuses will destroy access to the rest of the device. (refer

to the Design Security in Nonvolatile Flash and Antifuse

FPGAs white paper).

Look for this symbol to ensure your valuable IP is secure.

To ensure maximum security in Axcelerator devices, it is

recommended that the user program the device security

fuse (SFUS). When programmed, the Silicon Explorer II

testing probes are disabled to prevent internal probing,

and the programming interface is also disabled. All JTAG

public instructions are still accessible by the user.

For more information, refer to Actel’s Implementation of

Security in Actel Antifuse FPGAs application note.

Global Set Fuse

The Global Set Fuse determines if all R-cells and I/O

registers (InReg, OutReg, and EnReg) are either cleared

or preset by driving the GCLR and GPSET inputs of all R-

cells and I/O Registers (Figure 2-31 on page 2-47). Default

setting is to clear all registers (GCLR = 0 and GPSET =1) at

device power-up. When the GBSETFUS option is checked

during FUSE file generation, all registers are preset

(GCLR = 1 and GPSET= 0). A local CLR or PRESET will take

precedence over this setting. Both pins are pulled High

during normal device operation. For use details, see the

Libero IDE online help.

Figure 2-69 • FuseLock Logo

™

AX2000-1CS896M Datasheet(PDF) 104 Page - Actel Corporation

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