PCF8576C datasheet(21/56 Pages) NXP

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PCF8576C_9

Product data sheet

Rev. 09 — 9 July 2009

21 of 56

NXP Semiconductors

PCF8576C

Universal LCD driver for low multiplex rates

7.12 Data pointer

The addressing mechanism for the display RAM is realized using the data pointer. This

allows the loading of an individual display data byte or a series of display data bytes, into

any location of the display RAM. The sequence commences with the initialization of the

data pointer by the load data pointer command (see Table 13). After this, the data byte is

stored starting at the display RAM address indicated by the data pointer (see Figure 13).

Once each byte is stored, the data pointer is automatically incremented based on the

selected LCD conﬁguration.

The contents of the data pointer are incremented as follows:

• In static drive mode by eight.

• In 1:2 multiplex drive mode by four.

• In 1:3 multiplex drive mode by three.

• In 1:4 multiplex drive mode by two.

If an I2C-bus data access terminates early, the state of the data pointer is unknown.

Consequently, the data pointer must be rewritten prior to further RAM accesses.

7.13 Sub-address counter

The storage of display data is conditioned by the contents of the subaddress counter.

Storage is allowed to take place only when the contents of the subaddress counter match

with the hardware subaddress applied to A0, A1 and A2. The subaddress counter value is

deﬁned by the device select command (see Table 14). If the contents of the subaddress

counter and the hardware subaddress do not match then data storage is blocked but the

data pointer will be incremented as if data storage had taken place. The subaddress

counter is also incremented when the data pointer overﬂows.

The storage arrangements described lead to extremely efﬁcient data loading in cascaded

applications. When a series of display bytes are sent to the display RAM, automatic

wrap-over to the next PCF8576C occurs when the last RAM address is exceeded.

Subaddressing across device boundaries is successful even if the change to the next

device in the cascade occurs within a transmitted character (such as during the 14th

display data byte transmitted in 1:3 multiplex mode).

7.14 Bank selector

7.14.1 Output bank selector

The output bank selector (see Table 15), selects one of the four bits per display RAM

address for transfer to the display register. The actual bit selected depends on the LCD

drive mode in operation and on the instant in the multiplex sequence.

• In 1:4 multiplex mode: all RAM addresses of bit 0 are selected, followed sequentially

by the contents of bit 1, bit 2 and then bit 3.

• In 1:3 multiplex mode: bits 0, 1 and 2 are selected sequentially.

• In 1:2 multiplex mode: bits 0 and 1 are selected.

• In the static mode: bit 0 is selected.

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