PCF8576CUSLASH2 datasheet(23/56 Pages) NXP

23 / 56 page

PCF8576C_9

Product data sheet

Rev. 09 — 9 July 2009

23 of 56

NXP Semiconductors

PCF8576C

Universal LCD driver for low multiplex rates

Basic architecture

8.1 Characteristics of the I2C-bus

The I2C-bus provides bidirectional, two-line communication between different IC or

modules. The two lines are a Serial Data line (SDA) and a Serial Clock Line (SCL). When

connected to the output stages of a device, both lines must be connected to a positive

supply via a pull-up resistor. Data transfer is initiated only when the bus is not busy.

8.1.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse. Changes in the data line at this time will

be interpreted as a control signal. Bit transfer is illustrated in Figure 14.

8.1.1.1

START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW change

of the data line, while the clock is HIGH, is deﬁned as the START condition (S).

A LOW-to-HIGH change of the data line, while the clock is HIGH, is deﬁned as the STOP

condition (P). The START and STOP conditions are illustrated in Figure 15.

8.1.2 System conﬁguration

A device generating a message is a transmitter and a device receiving a message is the

receiver. The device that controls the message is the master and the devices which are

controlled by the master are the slaves. The system conﬁguration is illustrated in

Figure 16.

Fig 14. Bit transfer

mba607

data line

stable;

data valid

change

of data

allowed

SDA

SCL

Fig 15. Deﬁnition of START and STOP conditions

mbc622

SDA

SCL

STOP condition

SDA

SCL

START condition

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