PCF8576CUSLASH2 datasheet(25/56 Pages) NXP

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PCF8576C_9

Product data sheet

Rev. 09 — 9 July 2009

25 of 56

NXP Semiconductors

PCF8576C

Universal LCD driver for low multiplex rates

8.1.4 PCF8576C I2C-bus controller

The PCF8576C acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or

transmit data to an I2C-bus master receiver. The only data output from the PCF8576C are

the acknowledge signals of the selected devices. Device selection depends on the

I2C-bus slave address, the transferred command data and the hardware subaddress.

In single device application, the hardware subaddress inputs A0, A1 and A2 are normally

tied to VSS which deﬁnes the hardware subaddress 0. In multiple device applications

A0, A1 and A2 are tied to VSS or VDD using a binary coding scheme so that no two

devices with a common I2C-bus slave address have the same hardware subaddress.

In the power-saving mode it is possible that the PCF8576C is not able to keep up with the

highest transmission rates when large amounts of display data are transmitted. If this

situation occurs, the PCF8576C forces the SCL line LOW until its internal operations are

completed. This is known as the clock synchronization feature of the I2C-bus and serves

to slow down fast transmitters. Data loss does not occur.

8.1.5 Input ﬁlter

To enhance noise immunity in electrically adverse environments, RC low-pass ﬁlters are

provided on the SDA and SCL lines.

8.2 I2C-bus protocol

Two I2C-bus slave addresses (0111000 and 0111001) are reserved for the PCF8576C.

The least signiﬁcant bit of the slave address that a PCF8576C responds to is deﬁned by

the level tied at its input SA0. Therefore, two types of PCF8576C can be distinguished on

the same I2C-bus which allows:

• Up to 16 PCF8576Cs on the same I2C-bus for very large LCD applications.

• The use of two types of LCD multiplex on the same I2C-bus.

The I2C-bus protocol is shown in Figure 18. The sequence is initiated with a START

condition (S) from the I2C-bus master which is followed by one of the two PCF8576C

slave addresses available. All PCF8576Cs with the corresponding SA0 level acknowledge

in parallel with the slave address but all PCF8576Cs with the alternative SA0 level ignore

the whole I2C-bus transfer.

After acknowledgement, one or more command bytes (m) follow which deﬁne the status of

the addressed PCF8576Cs.

The last command byte is tagged with a cleared most signiﬁcant bit, the continuation bit C.

The command bytes are also acknowledged by all addressed PCF8576Cs on the bus.

After the last command byte, a series of display data bytes (n) may follow. These display

bytes are stored in the display RAM at the address speciﬁed by the data pointer and the

subaddress counter. Both data pointer and subaddress counter are automatically updated

and the data is directed to the intended PCF8576C device. The acknowledgement after

each byte is made only by the (A0, A1 and A2) addressed PCF8576C. After the last

display byte, the I2C-bus master issues a STOP condition (P).

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