PCF8576CUSLASH2 datasheet(24/56 Pages) NXP

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PCF8576C_9

Product data sheet

Rev. 09 — 9 July 2009

24 of 56

NXP Semiconductors

PCF8576C

Universal LCD driver for low multiplex rates

8.1.3 Acknowledge

The number of data bytes transferred between the START and STOP conditions from

transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge

bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during

which time the master generates an extra acknowledge related clock pulse.

Acknowledgement on the I2C-bus is illustrated in Figure 17.

• A slave receiver which is addressed must generate an acknowledge after the

reception of each byte.

• A master receiver must generate an acknowledge after the reception of each byte that

has been clocked out of the slave transmitter.

• The device that acknowledges must pull-down the SDA line during the acknowledge

clock pulse, so that the SDA line is stable LOW during the HIGH period of the

acknowledge related clock pulse (set-up and hold times must be taken into

consideration).

• A master receiver must signal an end-of-data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

master receiver must leave the data line HIGH during the 9th pulse to not

acknowledge. The master will now generate a STOP condition.

Fig 16. System conﬁguration

mga807

SDA

SCL

MASTER

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER

SLAVE

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

MASTER

TRANSMITTER/

RECEIVER

Fig 17. Acknowledgement on the I2C-bus

mbc602

START

condition

clock pulse for

acknowledgement

not acknowledge

acknowledge

data output

by transmitter

data output

by receiver

SCL from

master

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